公开(公告)号：US20230305965A1

公开(公告)日：2023-09-28

申请号：US18171565

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875

CPC classification number: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/683

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US11989131B2

公开(公告)日：2024-05-21

申请号：US18171565

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/0875 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/683

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US11080188B1

公开(公告)日：2021-08-03

申请号：US15939099

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： Jonathan Y. Tong ,  Ronald P. Hall ,  Christopher Colletti ,  David E. Kroesche ,  James N. Hardage, Jr.

IPC: G06F12/0815 ,  G06F12/1036 ,  G06F12/0808 ,  G06F12/1009

Abstract: A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.

公开(公告)号：US10922232B1

公开(公告)日：2021-02-16

申请号：US16400847

申请日：2019-05-01

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David E. Kroesche ,  David J. Williamson

IPC: G06F12/08 ,  G06F12/0873 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/0837

Abstract: An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.

公开(公告)号：US11886340B1

公开(公告)日：2024-01-30

申请号：US17818660

申请日：2022-08-09

Applicant: Apple Inc.

Inventor： Jonathan Y. Tong ,  David E. Kroesche ,  Brett S. Feero

IPC: G06F12/08 ,  G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/60

Abstract: A processor configured for real-time transaction processing is disclosed. A processor circuit includes configuration registers that designate a first range of physical memory addresses as reserved for real-time memory requests and a second, non-overlapping range of physical memory addresses that are shared between real-time and non-real-time memory requests. In response to determining that a memory request is associated with an address in the first range, the processor tags the request as a real-time request. The configuration registers may also store information designating portions of one or more cache memories and one or more buffers as being reserved for real-time memory requests. During arbitration, real-time memory requests are given priority over older, non-real-time memory requests.

公开(公告)号：US20220066941A1

公开(公告)日：2022-03-03

申请号：US17008491

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875 ,  G06F30/39

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US11586551B2

公开(公告)日：2023-02-21

申请号：US17008491

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US10552323B1

公开(公告)日：2020-02-04

申请号：US16126812

申请日：2018-09-10

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Todd A. Venton ,  Jonathan Y. Tong ,  David E. Kroesche

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0891 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0866

Abstract: Various embodiments of a method and apparatus for flushing a cache are disclosed. In a system, a cache memory is accessible by an execution circuit. The execution circuit executes instructions and may utilize data and/or instructions stored in the cache. A flush circuit is also coupled to the cache. Responsive to execution of a power down instruction by the execution circuit, the flush circuit performs a cache flush. If a control state is asserted in a control register, the flush circuit generates a dummy event upon completing the cache flush. Responsive to generating the dummy event, a processor core that includes the execution circuit is inhibited from being powered down.