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    Cache implementing multiple replacement policies
    4.
    发明授权
    Cache implementing multiple replacement policies 有权
    缓存实现多个替换策略

    公开(公告)号：US08719509B2

    公开(公告)日：2014-05-06

    申请号：US13755999

    申请日：2013-01-31

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F13/00

    CPC classification number: G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

    Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

    Abstract translation: 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。

    Cache Implementing Multiple Replacement Policies
    5.
    发明申请
    Cache Implementing Multiple Replacement Policies 有权
    缓存实现多个替换策略

    公开(公告)号：US20130151781A1

    公开(公告)日：2013-06-13

    申请号：US13755999

    申请日：2013-01-31

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F12/12 ,  G06F12/08

    CPC classification number: G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

    Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

    Abstract translation: 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。

    Power saving with dynamic pulse insertion
    6.
    发明授权
    Power saving with dynamic pulse insertion 有权

    公开(公告)号：US10270434B2

    公开(公告)日：2019-04-23

    申请号：US15046926

    申请日：2016-02-18

    Applicant: Apple Inc.

    Inventor： James Wang ,  Benjiman L. Goodman ,  Liang-Kai Wang ,  Robert D. Kenney

    IPC: H03K3/00 ,  H03K5/00 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329

    Abstract: A method and apparatus for saving power in integrated circuits is disclosed. An IC includes functional circuit blocks which are not placed into a sleep mode when idle. A power management circuit may monitor the activity levels of the functional circuit blocks not placed into a sleep mode. When the power management circuit detects that an activity level of one of the non-sleep functional circuit blocks is less than a predefined threshold, it reduce the frequency of a clock signal provided thereto by scheduling only one pulse of a clock signal for every N pulses of the full frequency clock signal. The remaining N−1 pulses of the clock signal may be inhibited. If a high priority transaction inbound for the functional circuit block is detected, an inserted pulse of the clock signal may be provided to the functional unit irrespective of when a most recent regular pulse was provided.

    Combined Transparent/Non-Transparent Cache
    8.
    发明申请
    Combined Transparent/Non-Transparent Cache 审中-公开
    组合透明/不透明缓存

    公开(公告)号：US20150149734A1

    公开(公告)日：2015-05-28

    申请号：US14611423

    申请日：2015-02-02

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F12/08

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

    Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。

    TRANSLATING CACHE HINTS
    9.
    发明申请
    TRANSLATING CACHE HINTS 有权
    翻译缓存提示

    公开(公告)号：US20140372699A1

    公开(公告)日：2014-12-18

    申请号：US13915911

    申请日：2013-06-12

    Applicant: Apple Inc.

    Inventor： Shailendra S. Desai ,  Gurjeet S. Saund ,  Deniz Balkan ,  James Wang

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0802 ,  G06F12/0888 ,  G06F12/12 ,  Y02D10/13

    Abstract: Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a transaction, and the first cache hint is compliant with a first protocol. The first cache hint can be set to a reserved encoding value as defined by the first protocol. Prior to the transaction being sent to the memory subsystem, the first cache hint is translated into a second cache hint. The memory subsystem recognizes cache hints which are compliant with a second protocol, and the second cache hint is compliant with the second protocol.

    Abstract translation: 用于翻译SoC中不同协议之间的缓存提示的系统和方法。 SoC中的请求代理生成用于事务的第一高速缓存提示，并且第一高速缓存提示符合第一协议。 第一个缓存提示可以设置为第一个协议定义的保留编码值。 在将事务发送到存储器子系统之前，第一高速缓存提示被转换成第二高速缓存提示。 存储器子系统识别符合第二协议的高速缓存提示，并且第二高速缓存提示符合第二协议。

    System cache with sticky removal engine
    10.
    发明授权
    System cache with sticky removal engine 有权
    系统缓存带粘性删除引擎

    公开(公告)号：US08886886B2

    公开(公告)日：2014-11-11

    申请号：US13629865

    申请日：2012-09-28

    Applicant: Apple Inc.

    Inventor： Sukalpa Biswas ,  Shinye Shiu ,  James Wang ,  Robert Hu

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/126 ,  G06F1/3225 ,  G06F12/0842

    Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.

    Abstract translation: 用于释放用于一个或多个组ID的高速缓存行的粘性状态的方法和装置。 粘性移除引擎遍历系统缓存的标签存储器，寻找与从系统高速缓存清除其高速缓存行的第一组ID的匹配。 引擎清除属于第一组ID的每个高速缓存行的粘性状态。 如果引擎接收到第二组ID的释放请求，则引擎记录当前索引以通过标记存储器记录其进度。 然后，引擎继续通过标签存储器查找与第一或第二组ID的匹配。 发动机卷绕到标签存储器的开头，并继续其行进直到达到第二组ID的记录索引。

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