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    Dynamic Allocation of Cache Memory as RAM
    6.
    发明申请
    Dynamic Allocation of Cache Memory as RAM 有权

    公开(公告)号：US20230067307A1

    公开(公告)日：2023-03-02

    申请号：US17462777

    申请日：2021-08-31

    Applicant: Apple Inc.

    Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

    IPC: G06F12/0802

    Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

    Memory Controller Reservation of Retry Queue
    7.
    发明申请
    Memory Controller Reservation of Retry Queue 有权

    公开(公告)号：US20250103520A1

    公开(公告)日：2025-03-27

    申请号：US18819755

    申请日：2024-08-29

    Applicant: Apple Inc.

    Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman ,  Brian P. Lilly ,  John H. Kelm ,  Rohit K. Gupta ,  Sandeep Gupta ,  Anwar Q. Rohillah

    IPC: G06F13/16 ,  G06F12/0831

    Abstract: A memory controller circuit receives memory access requests from a network of a computer system. Entries are reserved for these requests in a retry queue circuit. An arbitration circuit of the memory controller circuit issues those requests to a tag pipeline circuit that determines whether the received memory access requests hit in a memory cache. As a memory access request passes through the tag pipeline circuit, it may require another pass through this pipeline—for example, if resources such as certain storage circuits needed to complete the memory access request are unavailable (for example a snoop queue circuit). The reservation that has been made in the retry queue circuit thus keeps the request from having to be returned to the network for resubmission to the memory controller circuit if initial processing of the memory access request cannot be completed.

    Memory Controller Reservation of Resources for Cache Hit
    8.
    发明申请
    Memory Controller Reservation of Resources for Cache Hit 有权

    公开(公告)号：US20250103477A1

    公开(公告)日：2025-03-27

    申请号：US18819877

    申请日：2024-08-29

    Applicant: Apple Inc.

    Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman

    IPC: G06F12/02 ,  G06F12/0815 ,  G06F12/12

    Abstract: A memory controller circuit manages access to a memory cache circuit and storage circuits. The memory controller receives a memory access request, and attempts to reserve entries in a first set of storage circuits that are needed to process a cache hit prior to determining whether the memory access request hits in the memory cache circuit. This reservation attempt is performed without attempting to reserve other sets of storage circuits that are needed to process other possible outcomes of the memory access request, including a cache miss. If the memory controller circuit has successfully reserved entries in all of the first set of storage circuits, processing of the memory access request may be initiated. Conversely, if the memory controller is unable to reserve an entry in at least one of the first set of storage circuits, processing of the memory access request is inhibited.

    Configurable Interface Circuit
    9.
    发明申请
    Configurable Interface Circuit 有权

    公开(公告)号：US20230064369A1

    公开(公告)日：2023-03-02

    申请号：US17463292

    申请日：2021-08-31

    Applicant: Apple Inc.

    Inventor： Rohit K. Gupta ,  Rohit Natarajan ,  Jurgen M. Schulz ,  Harshavardhan Kaushikkar ,  Connie W. Cheung

    IPC: G06F12/0871 ,  G06F12/02 ,  G06F13/16 ,  H03K19/0175

    Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

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