公开(公告)号：US20240379438A1

公开(公告)日：2024-11-14

申请号：US18652947

申请日：2024-05-02

Applicant: Applied Materials, Inc.

Inventor： Veeraraghavan S. Basker ,  Kyoung Ha Kim ,  Byeong Chan Lee

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes combining selective recess of a sacrificial layer and isotropic etching of a silicon layer in order to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.

公开(公告)号：US20250112054A1

公开(公告)日：2025-04-03

申请号：US18894665

申请日：2024-09-24

Applicant: Applied Materials, Inc.

Inventor： Yuriy Shusterman ,  Sean Reidy ,  Sai Hooi Yeong ,  Lisa Megan McGill ,  Benjamin Colombeau ,  Andre P. Labonte ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/26 ,  H01L21/311

Abstract: Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the structure with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

公开(公告)号：US20250142957A1

公开(公告)日：2025-05-01

申请号：US18911689

申请日：2024-10-10

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Steven C.H. Hung ,  Veeraraghavan S. Basker ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan

IPC: H01L27/118

Abstract: Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs extending between a source region and a drain region, and the p-channel gate-all-around (p-GAA) field-effect transistor has a plurality of layers comprising in a range of from 5% to 15% germanium and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs.

公开(公告)号：US20250113577A1

公开(公告)日：2025-04-03

申请号：US18893455

申请日：2024-09-23

Applicant: Applied Materials, Inc.

Inventor： Veeraraghavan S. Basker ,  Sai Hooi Yeong ,  Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.

公开(公告)号：US20240332388A1

公开(公告)日：2024-10-03

申请号：US18609650

申请日：2024-03-19

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Benjamin Colombeau ,  Nicolas Breil ,  Ashish Pal ,  El Mehdi Bazizi ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan ,  Pratik B. Vyas ,  Gregory Costrini

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.