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    Clock Circuitry with Fault Detection
    2.
    发明申请
    Clock Circuitry with Fault Detection 审中-公开

    公开(公告)号：US20200241589A1

    公开(公告)日：2020-07-30

    申请号：US16256675

    申请日：2019-01-24

    Applicant: Arm Limited

    Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

    IPC: G06F1/10 ,  G06F1/08

    Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

    High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs
    3.
    发明授权
    High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs 有权

    公开(公告)号：US10452593B1

    公开(公告)日：2019-10-22

    申请号：US16027490

    申请日：2018-07-05

    Applicant: Arm Limited

    Inventor： Jamshed Jalal ,  Tushar P. Ringe ,  Ashok Kumar Tummala ,  Gurunath Ramagiri

    IPC: G06F13/42 ,  G06F12/0831 ,  G06F15/173

    Abstract: A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.

    Apparatus and method for routing access requests in an interconnect
    5.
    发明授权
    Apparatus and method for routing access requests in an interconnect 有权

    公开(公告)号：US11086802B1

    公开(公告)日：2021-08-10

    申请号：US16819566

    申请日：2020-03-16

    Applicant: Arm Limited

    Inventor： Jamshed Jalal ,  Tushar P. Ringe ,  Mark David Werkheiser ,  Gurunath Ramagiri

    IPC: G06F13/364 ,  G06F13/16 ,  G06F11/30 ,  G06F9/30 ,  G06F13/40

    Abstract: A technique is provided for routing access requests within an interconnect. An apparatus provides a plurality of requester elements for issuing access requests, and a slave element to be accessed in response to the access requests. An interconnect is used to couple the plurality of requester elements with the slave element, and provides an intermediate element that acts as a point of serialisation to order the access requests issued by the plurality of requester elements via the intermediate element. Communication channels are provided within the interconnect to support communication between each of the requester elements and the intermediate element, and between the intermediate element and the slave element. At least one requester element is a channel selectable requester element, and the interconnect further provides, for each channel selectable requester element, a bypass communication channel to support a direct communication between that channel selectable requester element and the slave element that bypasses the intermediate element. Each channel selectable requester element is then arranged, in the presence of a direct slave access condition, to issue an access request over the bypass communication channel to the slave element without that access request passing via the intermediate element.

    Snooping with access permissions
    6.
    发明授权
    Snooping with access permissions 有权

    公开(公告)号：US10942865B2

    公开(公告)日：2021-03-09

    申请号：US16440533

    申请日：2019-06-13

    Applicant: Arm Limited

    Inventor： Gurunath Ramagiri ,  Tushar P. Ringe ,  Mukesh Patel ,  Jamshed Jalal ,  Iat Pui Chan ,  Lakshmi Joga Vishnu Vardhan Badukonda

    IPC: G06F12/1081 ,  G06F12/0864 ,  G06F12/0877

    Abstract: A method and apparatus are provided to enable snoop forwarding to occur together with memory protection. A data processing apparatus in, for instance, the form of a home node forwards a snoop forwarding request on behalf of a requester to a target, the snoop forwarding request being capable of indicating one or more access permissions of the target in relation to the data. A further data processing apparatus in the form of, for instance, a receiver node may receive the snoop forwarding request and based on its own permissions that are provided in the snoop forwarding request, together with the state of the data, either provide a response back to the requester or the home node. In a still further data processing apparatus in the form of, for instance, a Memory Protection Unit (MPU), a regular snoop forwarding request made to a target in relation to data can be forwarded to the target or demoted to a non-forwarding snoop request based on the permissions of the target in relation to the data at the MPU.

    Snoop filter with imprecise encoding
    9.
    发明授权
    Snoop filter with imprecise encoding 有权

    公开(公告)号：US11567870B2

    公开(公告)日：2023-01-31

    申请号：US17215435

    申请日：2021-03-29

    Applicant: Arm Limited

    Inventor： Joshua Randall ,  Jamshed Jalal ,  Tushar P. Ringe ,  Jesse Garrett Beu

    IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/084

    Abstract: An apparatus comprises snoop filter storage circuitry to store snoop filter entries corresponding to addresses and comprising sharer information. Control circuitry selects which sharers, among a plurality of sharers capable of holding cached data, should be issued with snoop requests corresponding to a target address, based on the sharer information of the snoop filter entry corresponding to the target address. The control circuitry is capable of setting a given snoop filter entry corresponding to a given address to an imprecise encoding in which the sharer information provides an imprecise description of which sharers hold cached data corresponding to the given address, and the given snoop filter entry comprises at least one sharer count value indicative of a number of sharers holding cached data corresponding to the given address.

    Protocol layer tunneling for a data processing system
    10.
    发明授权
    Protocol layer tunneling for a data processing system 有权

    公开(公告)号：US11146495B2

    公开(公告)日：2021-10-12

    申请号：US16550018

    申请日：2019-08-23

    Applicant: Arm Limited

    Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Kishore Kumar Jagadeesha

    IPC: H04L12/863 ,  H04L12/801 ,  H04L12/835 ,  H04L12/46

    Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.

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