公开(公告)号：US20140189445A1

公开(公告)日：2014-07-03

申请号：US13728217

申请日：2012-12-27

申请人： Ashok Raj ,  John G. Holm ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mohan J. Kumar

发明人： Ashok Raj ,  John G. Holm ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mohan J. Kumar

IPC分类号： G06F11/00

CPC分类号： G06F11/006 ,  G06F11/0715 ,  G06F11/0772 ,  G06F11/0793

摘要： Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator.

摘要翻译： 公开了用于信令软件可恢复错误的发明的实施例。 在一个实施例中，处理器包括第一单元，可编程指示器和第二单元。 第一个单位是检测毒物的错误。 可编程指示灯是指示是否发出毒物误差作为机器检查错误或作为故障和系统管理中断之一发出信号。 第二个单元将响应于可编程指示器的毒性错误信号作为故障之一和系统管理错误。

公开(公告)号：US08671309B2

公开(公告)日：2014-03-11

申请号：US13175407

申请日：2011-07-01

申请人： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

发明人： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

IPC分类号： G06F11/00

CPC分类号： G06F11/0715 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/0793 ,  G06F2211/1088

摘要： Embodiments of a hardware processor including a plurality of machine state registers (MSRs) are described. At least one of the MSRs includes an erroring logical processing (ELP) bit which when set, indicates that a particular thread executing on the hardware processor caused an error.

摘要翻译： 描述了包括多个机器状态寄存器（MSR）的硬件处理器的实施例。 MSR中的至少一个包括错误的逻辑处理（ELP）位，当被设置时，指示在硬件处理器上执行的特定线程引起错误。

公开(公告)号：US20130007507A1

公开(公告)日：2013-01-03

申请号：US13175407

申请日：2011-07-01

申请人： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

发明人： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

IPC分类号： G06F11/00

CPC分类号： G06F11/0715 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/0793 ,  G06F2211/1088

摘要： Embodiments of a hardware processor including a plurality of machine state registers (MSRs) are described. At least one of the MSRs includes an erroring logical processing (ELP) bit which when set, indicates that a particular thread executing on the hardware processor caused an error.

摘要翻译： 描述了包括多个机器状态寄存器（MSR）的硬件处理器的实施例。 MSR中的至少一个包括错误的逻辑处理（ELP）位，当被设置时，指示在硬件处理器上执行的特定线程引起错误。

公开(公告)号：US07194540B2

公开(公告)日：2007-03-20

申请号：US09965295

申请日：2001-09-28

申请人： Anil Aggarwal ,  Oscar P. Pinto ,  Ashok Raj ,  Bruce M. Schlobohm ,  Rajesh R. Shah

发明人： Anil Aggarwal ,  Oscar P. Pinto ,  Ashok Raj ,  Bruce M. Schlobohm ,  Rajesh R. Shah

IPC分类号： G06F15/173

CPC分类号： H04L47/10 ,  H04L47/2425 ,  H04L49/101 ,  H04L49/30

摘要： A mechanism is provided at a host system to allow multiple entities (clients) to send and receive messages of a particular class of management services in a switched fabric for scalable solutions.

摘要翻译： 在主机系统处提供一种机制，以允许多个实体（客户机）在可交换结构中发送和接收特定类别的管理服务的消息以用于可扩展解决方案。

公开(公告)号：US20200174943A1

公开(公告)日：2020-06-04

申请号：US16206516

申请日：2018-11-30

申请人： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

发明人： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

IPC分类号： G06F12/1027 ,  G06F12/0864 ,  G06F13/16 ,  G06F9/38 ,  G06F11/22

摘要： In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

公开(公告)号：US20150113334A1

公开(公告)日：2015-04-23

申请号：US14057485

申请日：2013-10-18

申请人： Ashok Raj ,  Narayan Ranganathan

发明人： Ashok Raj ,  Narayan Ranganathan

IPC分类号： G06F11/07

CPC分类号： G06F11/079 ,  G06F11/0706 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/1417 ,  G06F2201/805

摘要： A computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.

摘要翻译： 计算系统可以包括包括当前值的机器检查计数器（MCC）。 当前值表示计算系统的系统重新启动重置硬件。 机器检查计数器包括一个特定于型号的寄存器，包括一个指示当前值的计数器，当系统重启时增加的当前值。

公开(公告)号：US07636832B2

公开(公告)日：2009-12-22

申请号：US11588900

申请日：2006-10-26

申请人： Ashok Raj ,  Rajesh Shah

发明人： Ashok Raj ,  Rajesh Shah

IPC分类号： G06F12/10

CPC分类号： G06F12/1081 ,  G06F12/126 ,  G06F2212/151 ,  G06F2212/683

摘要： Methods and apparatus to provide improved input/output (I/O) address translation lookaside buffer performance are described. In one embodiment, one or more entries of a cache (e.g., an I/O address translation lookaside buffer) are locked in response to a request to lock the one or more entries. Other embodiments are also described.

摘要翻译： 描述了提供改进的输入/输出（I / O）地址转换后备缓冲器性能的方法和装置。 在一个实施例中，响应于锁定一个或多个条目的请求来锁定高速缓存（例如，I / O地址转换后备缓冲器）的一个或多个条目。 还描述了其它实施例。

公开(公告)号：US20070079039A1

公开(公告)日：2007-04-05

申请号：US11241261

申请日：2005-09-30

申请人： Ashok Raj

发明人： Ashok Raj

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： Systems, methods, and apparatus to retarget platform interrupts in a reconfigurable system. Some embodiments include identifying each processor of a multiprocessor system capable of processing Corrected Platform Error Interrupts, adding each processor capable of processing Corrected Platform Error Interrupts to a list of potential Corrected Platform Error Interrupt targets, and updating an interrupt table with a target processor for an interrupt, wherein the interrupt table is accessible by an interrupt controller to target platform interrupts. Another embodiment includes receiving a request to disable the first processor in a multiprocessor apparatus, determining if the first processor is a Corrected Platform Error Interrupt destination, and determining if the second processor is capable of processing Corrected Platform Error Interrupts. This embodiment also includes reprogramming an interrupt controller to route interrupts to the second processor instead of the first processor and disabling the first processor.

摘要翻译： 重新定位可重构系统中的平台中断的系统，方法和设备。 一些实施例包括识别能够处理校正的平台错误中断的多处理器系统的每个处理器，将能够处理校正的平台错误中断的每个处理器添加到潜在的校正平台错误中断目标的列表中，以及用目标处理器更新中断表 中断，其中中断控制器可以访问中断表来定位平台中断。 另一实施例包括接收在多处理器设备中禁用第一处理器的请求，确定第一处理器是否是修正平台错误中断目的地，以及确定第二处理器是否能够处理校正的平台错误中断。 该实施例还包括重新编程中断控制器以将中断路由到第二处理器而不是第一处理器并禁用第一处理器。

公开(公告)号：US20150178142A1

公开(公告)日：2015-06-25

申请号：US14135570

申请日：2013-12-19

申请人： Ashok Raj ,  Mohan Kumar ,  Narayan Ranganathan

发明人： Ashok Raj ,  Mohan Kumar ,  Narayan Ranganathan

IPC分类号： G06F11/07

CPC分类号： G06F11/0793 ,  G06F11/0706 ,  G06F11/0766 ,  G06F11/0787 ,  G06F11/30 ,  G06F11/3003

摘要： A computing system can include a platform firmware to monitor hardware errors and to notify an operating system when a corrective action is to be performed to address a hardware error. The computing system can also include an extended error log to describe a hardware error. The computing system can further include an action record to direct the operating system to perform the corrective action to address the hardware error.

摘要翻译： 计算系统可以包括用于监视硬件错误的平台固件，并且当执行纠正措施以解决硬件错误时通知操作系统。 计算系统还可以包括扩展错误日志来描述硬件错误。 计算系统还可以包括动作记录，以指示操作系统执行纠正措施来解决硬件错误。

公开(公告)号：US20190042461A1

公开(公告)日：2019-02-07

申请号：US15958591

申请日：2018-04-20

申请人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

发明人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/38

摘要： A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.