公开(公告)号：US10784826B2

公开(公告)日：2020-09-22

申请号：US16169092

申请日：2018-10-24

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Christopher R. Bye ,  Vali Touba ,  Stephen J Creane

IPC: H03F1/14 ,  H03F3/21 ,  H03F3/19 ,  H03F1/02 ,  H03F3/68

Abstract: The present disclosure provide a device, system, and method for generating, in an electrical device, a 1 bit or a 0 bit that is received in a switching circuit powered by a battery. The device, system, and method generates, in the switching circuit, a negative bias voltage and a positive bias voltage. The device, system, and method transmits the negative bias voltage and the positive bias voltage to a power amplifier. The device, system, and method turns the power amplifier from an off-state to an on-state in response to receiving the negative bias voltage. The device, system, and method amplifies, with the power amplifier, a power signal moving through power amplifier when the amplifier is in the on-state.

公开(公告)号：US11581299B2

公开(公告)日：2023-02-14

申请号：US16817588

申请日：2020-03-12

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Daniel C. Boire ,  Kanin Chu ,  Hong M. Lu ,  Bernard J. Schmanski

IPC: H01L27/02 ,  H04B1/40 ,  H01L23/66

Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

公开(公告)号：US20200136571A1

公开(公告)日：2020-04-30

申请号：US16169092

申请日：2018-10-24

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Christopher R. Bye ,  Vali Touba ,  Stephen J Creane

IPC: H03F3/21 ,  H03F3/19 ,  H03F3/68 ,  H03F1/02

Abstract: The present disclosure provide a device, system, and method for generating, in an electrical device, a 1 bit or a 0 bit that is received in a switching circuit powered by a battery. The device, system, and method generates, in the switching circuit, a negative bias voltage and a positive bias voltage. The device, system, and method transmits the negative bias voltage and the positive bias voltage to a power amplifier. The device, system, and method turns the power amplifier from an off-state to an on-state in response to receiving the negative bias voltage. The device, system, and method amplifies, with the power amplifier, a power signal moving through power amplifier when the amplifier is in the on-state.

公开(公告)号：US20200294987A1

公开(公告)日：2020-09-17

申请号：US16817588

申请日：2020-03-12

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Daniel C. Boire ,  Kanin Chu ,  Hong M. Lu ,  Bernard J. Schmanski

IPC: H01L27/02 ,  H04B1/40 ,  H03H7/38 ,  H01L23/66

Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

公开(公告)号：US20190043709A1

公开(公告)日：2019-02-07

申请号：US14800387

申请日：2015-07-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Kanin Chu ,  Pane Chane Chao ,  Carlton T. Creamer

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/16 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L21/0254 ,  H01L21/0475 ,  H01L21/2007 ,  H01L21/2011 ,  H01L21/6835 ,  H01L21/76876 ,  H01L23/3732 ,  H01L27/1266 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L2221/68327

Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.