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    RESILIENT CONDUCTIVE BUMP FOR MICROELECTRONIC TESTING
    1.
    发明公开
    RESILIENT CONDUCTIVE BUMP FOR MICROELECTRONIC TESTING 审中-公开

    公开(公告)号：US20240339365A1

    公开(公告)日：2024-10-10

    申请号：US18297798

    申请日：2023-04-10

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Nathaniel P. Wyckoff ,  Jacob R. Mauermann ,  Mark E. Whiting

    IPC: H01L21/66 ,  G01R1/067

    CPC classification number: H01L22/30 ,  G01R1/067

    Abstract: A microelectronic component includes a substrate having at least one electrical pad, a resilient material on the substrate, and a conductive element on or in the resilient material and coupled to the at least one conductive pad. The resilient material may include, for instance, a compressible polymer. The conductive elements configured to be placed in contact with at least one test probe, where the resilient material is configured to be compressed by the at least one electrical probe into a deformed shape and where the resilient material is configured to return from the deformed shape to a non-deformed shape subsequent to a removal of the conductive element from contact with the at least one electrical probe.

    CAPACITOR STRUCTURE INTEGRATED WITH CONTACT PAD STRUCTURE
    2.
    发明申请
    CAPACITOR STRUCTURE INTEGRATED WITH CONTACT PAD STRUCTURE 有权

    公开(公告)号：US20250006779A1

    公开(公告)日：2025-01-02

    申请号：US18342963

    申请日：2023-06-28

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Nathaniel P. Wyckoff ,  Jacob R. Mauermann ,  Alexander S. Warren ,  William J. Klema

    IPC: H01G4/012 ,  H01G4/33 ,  H01L23/00 ,  H01L23/498 ,  H01G4/228

    Abstract: Integrated capacitor structures are described. In an example, an interconnect structure includes a first layer of conductive material and a second layer of conductive material. The first layer includes a first horizontal portion having a first opening and extending along a first horizontal plane, and a first vertical portion. The second layer includes a second horizontal portion having a second opening and extending along a second horizontal plane, and a second vertical portion. The interconnect structure also includes a dielectric extending along a third horizontal plane between the first and second horizontal portions, and having one or more openings. The first vertical component extends upward from the first horizontal portion, through one opening in the dielectric and the second opening of second layer, and the second vertical component extends downward from the second horizontal portion, through another opening in the dielectric and the first opening of first layer.

    ANISOTROPIC CONDUCTIVE SUBSTRATES AND METHODS OF USE
    3.
    发明申请
    ANISOTROPIC CONDUCTIVE SUBSTRATES AND METHODS OF USE 有权

    公开(公告)号：US20250071911A1

    公开(公告)日：2025-02-27

    申请号：US18452984

    申请日：2023-08-21

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： Nathaniel P. Wyckoff ,  Jacob R. Mauermann ,  Benjamin Terry ,  Justin D. Smith

    IPC: H05K3/36

    Abstract: A method fabricating at least one universal substrate from a batch product. The method includes steps of: providing a preform having a predetermined profile; wrapping a plurality of conductors about an outer surface of the preform; injecting a nonconductive matrix between conductors of the plurality of conductors, wherein the nonconductive matrix permeates between interstitial spaces of the plurality of conductors to isolate some conductors of the plurality of conductors from one another; forming the batch product that includes the plurality of conductors and the nonconductive matrix; and wafering at least one section of the batch product to form the at least one universal substrate. The plurality of conductors of the at least one universal substrate defines a first connection surface, a second connection surface opposite to the first connection surface, and a plurality of conductive pathways defined between the first connection surface and the second connection surface.

    INLINE RESISTOR INTEGRATED WITH CONDUCTIVE CONTACT PAD STRUCTURE
    4.
    发明申请
    INLINE RESISTOR INTEGRATED WITH CONDUCTIVE CONTACT PAD STRUCTURE 有权

    公开(公告)号：US20240413111A1

    公开(公告)日：2024-12-12

    申请号：US18206731

    申请日：2023-06-07

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Nathaniel P. Wyckoff ,  Alexander S. Warren ,  Jacob R. Mauermann ,  Justin D. Smith

    IPC: H01L23/00

    Abstract: An integrated circuit structure includes (i) a first layer including a first metal, (ii) a second layer above and in contact with the first layer, the second layer including a resistive material, and (iii) a third layer above and in contact with the second layer, the third layer including a second metal. In an example, the resistive material is different from one or both the first metal and the second metal. An interconnect component is above and in contact with the second layer. In an example, the interconnect component is a solder bump or a solder ball. In an example, a resistivity of the resistive material of the second layer is at least 20%, or at least 50% greater than a resistivity of each of the first and third layers. In an example, the resistive material includes a third metal different from the first and second metals and/or a metalloid.

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