公开(公告)号：US20240347409A1

公开(公告)日：2024-10-17

申请号：US18747798

申请日：2024-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Sangkyu Lee ,  Yongkoon Lee ,  Seokkyu Choi

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.

公开(公告)号：US20240178122A1

公开(公告)日：2024-05-30

申请号：US18226352

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Sangjin BAEK ,  Kyoung Lim SUK ,  Shang-Hoon SEO ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311

Abstract: A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.

公开(公告)号：US20240153860A1

公开(公告)日：2024-05-09

申请号：US18069290

申请日：2022-12-21

Applicant: InnoLux Corporation

Inventor： Te-Hsun LIN ,  Wen-Hsiang LIAO ,  Yung-Feng CHEN ,  Ming-Hsien SHIH

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49844 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L23/49833 ,  H01L2224/16013 ,  H01L2224/16105 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/182 ,  H01L2924/35121

Abstract: An electronic device is provided. The electronic device includes a redistribution structure, an electronic unit and a first conductive pad. The first conductive pad is disposed between the redistribution structure and the electronic unit. The electronic unit is electrically connected to the redistribution structure through the first conductive pad. The first conductive pad has a first coefficient of thermal expansion and a first Young's modulus. The first coefficient of thermal expansion and the first Young's modulus conform to the following formula: 0.7×(0.0069E2−1.1498E+59.661)≤CTE≤1.3×(0.0069E2−1.1498E+59.661), wherein CTE is the first coefficient of thermal expansion, and E is the first Young's modulus in the formula.

公开(公告)号：US20240096732A1

公开(公告)日：2024-03-21

申请号：US18154329

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao CHEN ,  Li-Hui CHENG ,  Ying-Ching SHIH

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/3675 ,  H01L23/49833 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H10B80/00 ,  H01L24/73 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29193 ,  H01L2224/32221 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.

公开(公告)号：US20240063078A1

公开(公告)日：2024-02-22

申请号：US18497043

申请日：2023-10-30

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO ,  Chun-Yin LIN

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/367 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/162 ,  H01L24/48 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/16157 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48225 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/19011 ,  H01L2924/19041

Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second semiconductor die, a thermal spreader, a molding material, and a second redistribution layer. The first semiconductor die and the second semiconductor die are disposed side-by-side over the first redistribution layer. The thermal spreader vertically overlaps with the first semiconductor die and/or the second semiconductor die. The molding material surrounds the thermal spreader, the first semiconductor die and the second semiconductor die. The second redistribution layer is disposed over the molding material.

公开(公告)号：US11901343B2

公开(公告)日：2024-02-13

申请号：US17233983

申请日：2021-04-19

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Bora Baloglu ,  Ron Huemoeller ,  Curtis Zwenger

IPC: H01L23/495 ,  H01L25/10 ,  H01L23/373 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/552 ,  H01L23/00 ,  H01L23/367 ,  H01L23/36 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13082 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/14335 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.

公开(公告)号：US20240047436A1

公开(公告)日：2024-02-08

申请号：US17880687

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Hao-Yi Tsai ,  Kris Lipu Chuang ,  Hsin-Yu Pan

IPC: H01L25/10 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1094 ,  H01L2225/1058 ,  H01L24/73

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a first die disposed on and electrically coupled to a first redistribution structure and laterally covered by a first insulating encapsulation, a second die disposed over the first die and laterally covered by a second insulating encapsulation, a second redistribution structure interposed between and electrically coupled to the first and second dies, a third redistribution structure disposed on the second die and opposite to the second redistribution structure, and at least one thermal-dissipating feature embedded in a dielectric layer of the third redistribution structure and electrically isolated from a patterned conductive layer of the third redistribution structure through the dielectric layer. Through substrate vias of the first die are physically connected to the second redistribution structure or the first redistribution structure. The thermal-dissipating feature is thermally coupled to a back surface of the second die.

公开(公告)号：US20230411237A1

公开(公告)日：2023-12-21

申请号：US18258190

申请日：2021-03-11

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Shuzo AKEJIMA

IPC: H01L23/367 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L23/5383 ,  H01L2225/1094 ,  H01L25/0655 ,  H01L23/5386

Abstract: A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member.

公开(公告)号：US20230307309A1

公开(公告)日：2023-09-28

申请号：US18200173

申请日：2023-05-22

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/36 ,  H05K7/20 ,  H01L23/42 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/36 ,  H05K7/2039 ,  H01L23/42 ,  H01L23/49822 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L25/0657 ,  H05K2201/10378 ,  H01L2225/1094 ,  H01L2225/107 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/73204

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermal management layer disposed between the first and second devices. The thermal management layer may be configured to reduce heat transfer between the first and second devices.

公开(公告)号：US11721560B2

公开(公告)日：2023-08-08

申请号：US17402595

申请日：2021-08-15

Applicant: InnoLux Corporation

Inventor： Chia-Chieh Fan ,  Chin-Lung Ting ,  Cheng-Chi Wang ,  Ming-Tsang Wu

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L21/568 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/97 ,  H01L25/50 ,  H01L23/3128 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/12105 ,  H01L2224/95001 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/18162 ,  H01L2924/3511

Abstract: A manufacturing method of semiconductor device includes providing a substrate, forming a sacrificial layer on the substrate, forming a resin layer on the sacrificial layer, disposing first chips on the sacrificial layer, and forming a first dielectric layer having trenches and surrounding the first chips, wherein an upper surface of the first dielectric layer and an upper surface of the resin layer are at a same plane.