Abstract:
1,125,332. Digital electric computer. WESTERN ELECTRIC CO. Inc. 14 Oct., 1965 [14 Oct., 1964], No. 43551/65. Heading G4A. [Also in Division H4] A program controlled data processing system comprises a memory arrangement containing sequences of program order words and data, a control arrangement controlling the transfer of words to and from the memory, executing the sequences of program order words and generating command signals, and an inputoutput system responsive to the command signals, wherein the memory arrangement comprises a first portion containing sequences of program order words and certain fixed data, and a second portion containing data defining the functional assignment of word locations of another portion of the memory arrangement and equipment configurations defining the inputoutput system. The processing system is arranged to control a telephone switching system office while being adaptable to cater for the characteristics of different offices. A generic program suitable for all offices of a particular class is employed for all offices of that class and is tailored to specific offices by means o f office parameters which are stored in the memory apart from the generic program, the parameters defining the features of the office, and the hardware and office code translation information which is unique to the lines and tracks of the office. Thus changes required on consequent growth of the office are generally limited to the parameters stored. The generic program is located by the manufacturer in a fixed location and is not changed. Mutually exclusive programs e.g. programs determined by office concentration ratios are also stored in a fixed location as also are areas (3) and (4). The other data shown in Fig. 6, comprising the program store, deal with the office parameters including the particular translations required by the office and also initialize information in a call store (Fig. 7) which is an electrically alterable memory and contains the more rapidly changing data system.
Abstract:
A program-controlled data-processing system in which ''''threecycle overlap'''' execution of program instructions is employed. The processor comprises three circuit arrangements which are concurrently operative with respect to three successive program order words. Each order word which is executed by the control arrangement is first brought into one circuit arrangement (the Buffer Order Word Register) and at a discrete time thereafter each instruction is moved to a second circuit arrangement (the Order Word Register). While the order word is in the Buffer Order Word Register, the instruction portion of the order word is decoded by a corresponding decoder circuit (the Buffer Order Word Decoder) and while it resides in the Order Word Register the instruction portion of the order word is decoded by a second decoder, namely, the Order Word Decoder. The third circuit arrangement serves to transmit commands to the program store to obtain a next succeeding order word from the Buffer Order Word Register.
Abstract:
Improvements in data processor systems to increase data handling capabilities and to conserve memory space. The improvements are accomplished by parallel execution of independent data processing actions, by providing single cycle execution of functions which customarily require several program steps, and by optimizing the use of instruction code space and data space in memory.
Abstract:
A program controlled telephone switching system is shown as an example of a real time program controlled data processing system. The system work functions of the telephone switching system are performed at assigned levels of a priority hierarchy. This hierarchy includes a base level at which routine jobs are performed, timed interrupt levels at which input-output jobs, which require a fair degree of timing precision, are performed and a plurality of trouble interrupt levels (maintenance interrupt levels), which are employed to initiate remedial actions in accordance with a prescribed remedial plan. The telephone functions which are performed at the base level are allocated processor time in accordance with a base level executive program frequency table. The base level executive program provides time for execution of certain low priority maintenance functions. In the absence of trouble the processor time is shared by the timed interrupt level programs and the base level programs. The trouble interrupt programs are initiated upon the detection of corresponding classes of trouble.