Program controlled data processing system
    1.
    发明授权
    Program controlled data processing system 失效
    程序控制数据处理系统

    公开(公告)号:US3651480A

    公开(公告)日:1972-03-21

    申请号:US3651480D

    申请日:1967-11-24

    Abstract: A program controlled data processor system which employs functionally equivalent first and second control units on a mutually exclusive basis to control an input-output system. The processor system comprises a plurality of independent memory units and communication between the control means and the independent memory units is by way of communication paths which may be selectively associated with any of the memory units and with either of the control means. The processor arrangement includes means for insuring that the two control means simultaneously carry out identical work functions.

    Abstract translation: 一种程序控制的数据处理器系统,其在相互排斥的基础上采用功能上等效的第一和第二控制单元来控制输入 - 输出系统。 处理器系统包括多个独立的存储器单元,并且控制装置和独立存储器单元之间的通信是通过可以选择性地与任何存储器单元和控制装置中的任何一个相关联的通信路径。 处理器装置包括用于确保两个控制装置同时执行相同功能的装置。

    Program controlled data processing system
    4.
    发明授权
    Program controlled data processing system 失效
    程序控制数据处理系统

    公开(公告)号:US3568157A

    公开(公告)日:1971-03-02

    申请号:US3568157D

    申请日:1967-11-24

    Abstract: A program controlled telephone switching system is shown as an example of a real time program controlled data processing system. The system work functions of the telephone switching system are performed at assigned levels of a priority hierarchy. This hierarchy includes a base level at which routine jobs are performed, timed interrupt levels at which input-output jobs, which require a fair degree of timing precision, are performed and a plurality of trouble interrupt levels (maintenance interrupt levels), which are employed to initiate remedial actions in accordance with a prescribed remedial plan. The telephone functions which are performed at the base level are allocated processor time in accordance with a base level executive program frequency table. The base level executive program provides time for execution of certain low priority maintenance functions. In the absence of trouble the processor time is shared by the timed interrupt level programs and the base level programs. The trouble interrupt programs are initiated upon the detection of corresponding classes of trouble.

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