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    Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature
    1.
    发明授权
    Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature 有权
    写入驱动电路，用于根据环境温度控制施加到相变存储器的写入电流

    公开(公告)号：US07447092B2

    公开(公告)日：2008-11-04

    申请号：US11079198

    申请日：2005-03-15

    申请人： Baek-Hyung Cho ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Byung-Gil Choi

    发明人： Baek-Hyung Cho ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Byung-Gil Choi

    IPC分类号： G11C7/04

    CPC分类号： G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0078

    摘要： A programming method which controls the amount of a write current applied TO Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the phase change material (PCM) in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing or keeping the same a reset current and/or a set current.

    摘要翻译： 控制施加到TO相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。 编程方法包括保持在较高电阻状态下的PCM的电阻与相变材料（PCM）的电阻在较低电阻状态下的比率恒定或基本恒定，而与环境温度无关。 可以通过增加，减少或保持复位电流和/或设定电流来保持该比率。

    Phase-changeable memory device and read method thereof
    5.
    发明授权
    Phase-changeable memory device and read method thereof 有权
    相变存储器件及其读取方法

    公开(公告)号：US07391644B2

    公开(公告)日：2008-06-24

    申请号：US11605212

    申请日：2006-11-29

    申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

    摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

    Memory system including a resistance variable memory device
    6.
    发明授权
    Memory system including a resistance variable memory device 有权
    存储器系统包括电阻变量存储器件

    公开(公告)号：US07668007B2

    公开(公告)日：2010-02-23

    申请号：US12124523

    申请日：2008-05-21

    申请人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    发明人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

    摘要翻译： 存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控​​制器。 电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电 位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平 高电压。

    RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF
    7.
    发明申请
    RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF 有权
    电阻可变存储器件及其读取方法

    公开(公告)号：US20080232161A1

    公开(公告)日：2008-09-25

    申请号：US12124523

    申请日：2008-05-21

    申请人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    发明人： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

    摘要翻译： 存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控​​制器。 电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电 位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平 高电压。

    Phase-changeable memory device and read method thereof
    8.
    发明申请
    Phase-changeable memory device and read method thereof 有权
    相变存储器件及其读取方法

    公开(公告)号：US20070133271A1

    公开(公告)日：2007-06-14

    申请号：US11605212

    申请日：2006-11-29

    申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

    摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

    Semiconductor memory device capable of compensating for leakage current
    9.
    发明授权
    Semiconductor memory device capable of compensating for leakage current 有权
    能够补偿漏电流的半导体存储器件

    公开(公告)号：US07248494B2

    公开(公告)日：2007-07-24

    申请号：US11220294

    申请日：2005-09-06

    申请人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

    发明人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

    IPC分类号： G11C11/00

    CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

    摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

    摘要翻译： 半导体存储器件补偿漏电流。 多个存储单元设置在字线和位线的交点处。 多个虚拟单元被连接到至少一个虚拟位线。 泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。 读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。 存储器件是包含相变材料的相变存储器件。 半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

    Semiconductor memory device capable of compensating for leakage current
    10.
    发明申请
    Semiconductor memory device capable of compensating for leakage current 有权
    能够补偿漏电流的半导体存储器件

    公开(公告)号：US20060050548A1

    公开(公告)日：2006-03-09

    申请号：US11220294

    申请日：2005-09-06

    申请人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

    发明人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

    IPC分类号： G11C11/00

    CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

    摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

    摘要翻译： 半导体存储器件补偿漏电流。 多个存储单元设置在字线和位线的交点处。 多个虚拟单元被连接到至少一个虚拟位线。 泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。 读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。 存储器件是包含相变材料的相变存储器件。 半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。