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公开(公告)号：US07099187B2
公开(公告)日：2006-08-29
申请号：US11225953
申请日：2005-09-14
Applicant: Bin Li , Kenneth R. Knowles , David C. Lawson
Inventor： Bin Li , Kenneth R. Knowles , David C. Lawson
IPC: G11C11/00
CPC classification number: G11C13/0004 , G11C13/0038 , G11C13/004
Abstract: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.
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公开(公告)号：US06965521B2
公开(公告)日：2005-11-15
申请号：US10631174
申请日：2003-07-31
Applicant: Bin Li , Kenneth R. Knowles , David C. Lawson
Inventor： Bin Li , Kenneth R. Knowles , David C. Lawson
CPC classification number: G11C13/0004 , G11C13/0038 , G11C13/004
Abstract: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.
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3.发明授权公开(公告)号：US06215694B1
公开(公告)日：2001-04-10
申请号：US09553595
申请日：2000-04-20
Applicant: Bin Li , Livia L. Zien , David C. Lawson , Tatia B. Butts , Tri M. Hoang
Inventor： Bin Li , Livia L. Zien , David C. Lawson , Tatia B. Butts , Tri M. Hoang
IPC: G11C1100
CPC classification number: G11C11/4125
Abstract: A single event upset hardened multiport memory cell to be utilized in a register file is disclosed. The single event upset hardened multiport memory cell includes a storage cell, a write bitline, a read bitline. The storage cell, which is utilized for storing data, includes first and second sets of cross-coupled transistors and first and second sets of isolation transistors. The first and second sets of isolation transistors are respectively coupled to the first and second set of cross-coupled transistors such that two inversion paths are formed between the two sets of cross-coupled transistors and the two sets of isolation transistors. Coupled to the storage cell, the write bitline inputs write data to the storage cell. Also coupled to the storage cell, the read bitline outputs read data from the storage cell.
Abstract translation: 公开了一种用于寄存器文件中的单事件硬化多端口存储单元。 单事件硬化多端口存储单元包括存储单元，写位线，读位线。 用于存储数据的存储单元包括第一组和第二组交叉耦合晶体管和第一组和第二组隔离晶体管。 第一和第二组隔离晶体管分别耦合到第一和第二组交叉耦合晶体管，使得在两组交叉耦合晶体管和两组隔离晶体管之间形成两个反转路径。 耦合到存储单元，写位线输入将数据写入存储单元。 读取位线也耦合到存储单元，从存储单元输出读取数据。
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公开(公告)号：US06944041B1
公开(公告)日：2005-09-13
申请号：US10811454
申请日：2004-03-26
Applicant: Bin Li , Kenneth R. Knowles , David C. Lawson
Inventor： Bin Li , Kenneth R. Knowles , David C. Lawson
CPC classification number: G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0069
Abstract: A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.
Abstract translation: 公开了一种用于访问硫族化物存储器阵列的电路。 硫族化物存储器阵列包括具有由硫族化物存储元件形成的行和列的多个子阵列。 硫族化物存储器阵列由离散读和写电路访问。 与相应的一个子阵列相关联，每个写入电路包括独立的写入0电路和独立的写入1电路。 还与相应的一个子阵列相关联，每个读取电路包括读出放大器电路。 此外，电压电平控制模块耦合到读取和写入电路，以确保在读取和写入操作期间跨硫族化物存储器阵列内的硫族化物存储元件的电压不超过预定值。
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公开(公告)号：US06327176B1
公开(公告)日：2001-12-04
申请号：US09844079
申请日：2001-04-26
Applicant: Bin Li , David C. Lawson
Inventor： Bin Li , David C. Lawson
IPC: G11C11412
CPC classification number: G11C11/4125
Abstract: A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.
Abstract translation: 公开了一种单件事件硬化锁定电路。 单事件硬化锁存电路包括第一双端口反相器和第二双端口反相器。 输入端通过第一组通道门耦合到第一双端口逆变器。 第一个双端口逆变器通过第二组通孔连接到第二个双端口逆变器。 输出端连接到第一和第二双端口逆变器。
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Patent Agency Ranking
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公开(公告)号：USD1026346S1
公开(公告)日：2024-05-07
申请号：US29863779
申请日：2022-12-22
Applicant: Bin Li
Designer： Bin Li
Abstract: FIG. 1 is a front, right and top perspective view of a pet feeder, showing my new design;
FIG. 2 is a rear, left and bottom perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top plan view thereof; and,
FIG. 8 is a bottom plan view thereof.-
公开(公告)号：US20220326999A1
公开(公告)日：2022-10-13
申请号：US17853564
申请日：2022-06-29
Applicant: Drew Penney , Bin Li , Tsung-Yuan Tai , Anna Drewek-Ossowicka , Rameshkumar Illikkal , Andrew J. Herdrich , Jaroslaw Sydir
Inventor： Drew Penney , Bin Li , Tsung-Yuan Tai , Anna Drewek-Ossowicka , Rameshkumar Illikkal , Andrew J. Herdrich , Jaroslaw Sydir
IPC: G06F9/50
Abstract: Apparatuses, methods, and systems for dynamic resource allocation based on quality-of-service prediction are disclosed. In embodiments, an apparatus includes quality-of-service prediction circuitry and a resource controller. The quality-of-service prediction circuitry is to make quality-of-service predictions using a model based at least in part on at least one performance counter measurements and at least one quality-of-service measurement. The resource controller is to allocate one or more shared resources based on the quality-of-service predictions and architectural performance counter measurements.
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公开(公告)号：US20220125226A1
公开(公告)日：2022-04-28
申请号：US17083218
申请日：2020-10-28
Applicant: Bin Li
Inventor： Bin Li
Abstract: This utility model released one kind of multifunctional flexibly transformable cup, comprising one internally cut-through transformable cup and a nested bottom plug that is sealed and clamped with the transformable cup body. The above-mentioned transformable cup is comprised of a foldable enclosure and pin that are successively cut-through and flexibly and tightly connected. The aforesaid seal clamp for embedded bottom plug is located at the junction between the foldable enclosure and pin. When the multifunctional flexibly transformable cup of the utility model is in use, the folding enclosure body can be overturned freely, and the whole body is made of food-grade flexible silica gel material, which is safe and reliable and not easy to be broken. It can also be used as the wine cup, bottle stopper and the bottleneck inserted into the wine bottle that can be directly used for drainage of fluid, with complete functions.
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公开(公告)号：US10924743B2
公开(公告)日：2021-02-16
申请号：US15549261
申请日：2015-02-06
Applicant: Microsoft Technology Licensing, LLC , Bin Li , Jizheng Xu
Inventor： Bin Li , Jizheng Xu
IPC: H04N19/132 , H04N19/119 , H04N19/52 , H04N19/172 , H04N19/147 , H04N19/127 , H04N19/176 , H04N19/61 , H04N19/70
Abstract: Various innovations in media encoding are presented herein. In particular, the innovations can reduce the computational complexity of encoding by selectively skipping certain evaluation stages during encoding. For example, based on analysis of decisions made earlier in encoding or based on analysis of media to be encoded, an encoder can selectively skip evaluation of certain coding tools (such as residual coding or rate-distortion-optimized quantization), skip evaluation of certain values for parameters or settings (such as candidate unit sizes or transform sizes, or candidate partition patterns for motion compensation), and/or skip evaluation of certain coding modes (such as frequency transform skip mode) that are not expected to improve rate-distortion performance during encoding.
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