公开(公告)号：US20130009236A1

公开(公告)日：2013-01-10

申请号：US13543312

申请日：2012-07-06

申请人： Bongyong Lee ,  Sang-Hoon Kim ,  Ae-Jeong Lee ,  Dongchan Kim

发明人： Bongyong Lee ,  Sang-Hoon Kim ,  Ae-Jeong Lee ,  Dongchan Kim

IPC分类号： H01L29/78

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

摘要翻译： 存储器件包括在衬底上平行延伸的多个细长栅极叠层和设置在相邻栅极叠层之间沟槽中的至少一个绝缘区域。 所述至少一个绝缘区具有具有第一宽度的线性第一部分和具有大于第一宽度的第二宽度的加宽的第二部分。 公共源极区域设置在至少一个绝缘区域下方的衬底中。 这些器件还包括各自的导电插塞，其穿过至少一个绝缘区域的加宽的第二部分中的相应导电插塞并且电连接到公共源极区域，以及设置在相邻栅极叠层之间的导电插塞上的至少一个捆扎线 并与导电插头直接接触。

公开(公告)号：US08803222B2

公开(公告)日：2014-08-12

申请号：US13543312

申请日：2012-07-06

申请人： Bongyong Lee ,  Sang-Hoon Kim ,  Ae-Jeong Lee ,  Dongchan Kim

发明人： Bongyong Lee ,  Sang-Hoon Kim ,  Ae-Jeong Lee ,  Dongchan Kim

IPC分类号： H01L29/792

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

摘要翻译： 存储器件包括在衬底上平行延伸的多个细长栅极叠层和设置在相邻栅极叠层之间沟槽中的至少一个绝缘区域。 所述至少一个绝缘区具有具有第一宽度的线性第一部分和具有大于第一宽度的第二宽度的加宽的第二部分。 公共源极区域设置在至少一个绝缘区域下方的衬底中。 这些器件还包括各自的导电插塞，其穿过至少一个绝缘区域的加宽的第二部分中的相应导电插塞并且电连接到公共源极区域，以及设置在相邻栅极叠层之间的导电插塞上的至少一个捆扎线 并与导电插头直接接触。

公开(公告)号：US20130215679A1

公开(公告)日：2013-08-22

申请号：US13772868

申请日：2013-02-21

申请人： Ae-Jeong Lee ,  Bongyong Lee ,  Dongchan Kim ,  Jaesung Sim

发明人： Ae-Jeong Lee ,  Bongyong Lee ,  Dongchan Kim ,  Jaesung Sim

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3409 ,  H01L27/1157 ,  H01L27/11582

摘要： A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.

摘要翻译： 一种在非易失性存储器件中调整接地选择晶体管的阈值电压的方法包括：在读取操作中向第一接地选择晶体管的栅极提供第一电压，并向第二接地选择晶体管的栅极提供第二电压， 读操作。 非易失性存储器件包括至少一个串，串具有串选择晶体管，存储单元以及串联连接并堆叠在基板上的第一和第二接地选择晶体管。

公开(公告)号：US08293618B2

公开(公告)日：2012-10-23

申请号：US12551311

申请日：2009-08-31

申请人： Dongchan Kim ,  Sungkweon Baek

发明人： Dongchan Kim ,  Sungkweon Baek

IPC分类号： H01L21/762 ,  H01L21/20

CPC分类号： H01L21/76224 ,  H01L27/11521 ,  H01L29/66825

摘要： A method of forming a semiconductor device includes forming a trench on a semiconductor substrate to define an active region, forming a radical oxide layer on a sidewall and a bottom surface of the trench, and forming a nitride layer on the radical oxide layer. The conduction band offset of the radical oxide layer is greater than the conduction band offset of a thermal oxide layer having the same thickness as the radical oxide layer.

摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成沟槽以限定有源区，在沟槽的侧壁和底表面上形成自由基氧化物层，以及在自由基氧化物层上形成氮化物层。 自由基氧化物层的导带偏移大于具有与自由基氧化物层相同厚度的热氧化物层的导带偏移。

公开(公告)号：US20100075479A1

公开(公告)日：2010-03-25

申请号：US12551311

申请日：2009-08-31

申请人： Dongchan Kim ,  Sungkweon Baek

发明人： Dongchan Kim ,  Sungkweon Baek

IPC分类号： H01L21/762 ,  H01L21/20 ,  H01L21/28

CPC分类号： H01L21/76224 ,  H01L27/11521 ,  H01L29/66825

摘要： A method of forming a semiconductor device includes forming a trench on a semiconductor substrate to define an active region, forming a radical oxide layer on a sidewall and a bottom surface of the trench, and forming a nitride layer on the radical oxide layer. The conduction band offset of the radical oxide layer is greater than the conduction band offset of a thermal oxide layer having the same thickness as the radical oxide layer.

摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成沟槽以限定有源区，在沟槽的侧壁和底表面上形成自由基氧化物层，以及在自由基氧化物层上形成氮化物层。 自由基氧化物层的导带偏移大于具有与自由基氧化物层相同厚度的热氧化物层的导带偏移。