公开(公告)号：US09595333B2

公开(公告)日：2017-03-14

申请号：US14702895

申请日：2015-05-04

申请人： Jaesung Sim ,  Youngwoo Park

发明人： Jaesung Sim ,  Youngwoo Park

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24

摘要： According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage.

摘要翻译： 根据示例性实施例，非易失性存储器件包括在水平半导体层上的多个单元串。 每个单元串包括在与水平半导体层垂直的方向上堆叠的多个存储单元。 根据示例实施例，非易失性存储器件的编程方法包括设置与单元串对应的位线，设置连接到单元串的多个串选择线，以及向接地选择线施加较低的负电压。 接地选择线连接到存储器单元和半导体层之间的多个接地选择晶体管。 字符串选择行在与位线相交的方向上延伸。 负电压低于接地电压。

公开(公告)号：US20160027514A1

公开(公告)日：2016-01-28

申请号：US14702895

申请日：2015-05-04

申请人： Jaesung SIM ,  Youngwoo PARK

发明人： Jaesung SIM ,  Youngwoo PARK

IPC分类号： G11C16/10 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24

摘要： According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage.

摘要翻译： 根据示例性实施例，非易失性存储器件包括在水平半导体层上的多个单元串。 每个单元串包括在与水平半导体层垂直的方向上堆叠的多个存储单元。 根据示例实施例，非易失性存储器件的编程方法包括设置与单元串对应的位线，设置连接到单元串的多个串选择线，以及向接地选择线施加较低的负电压。 接地选择线连接到存储器单元和半导体层之间的多个接地选择晶体管。 字符串选择行在与位线相交的方向上延伸。 负电压低于接地电压。

公开(公告)号：US20150145015A1

公开(公告)日：2015-05-28

申请号：US14519713

申请日：2014-10-21

申请人： Yoocheol Shin ,  Hongsoo Kim ,  Jaesung Sim

发明人： Yoocheol Shin ,  Hongsoo Kim ,  Jaesung Sim

IPC分类号： H01L27/115

CPC分类号： H01L27/11556 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

摘要翻译： 三维半导体存储器件包括堆叠结构，垂直半导体图案，公共源极区域和阱拾取区域。 堆叠结构设置在第一导电类型的半导体层上。 每个堆叠结构包括彼此垂直堆叠并沿第一方向延伸的电极。 垂直半导体图案穿透层叠结构。 第二导电类型的公共源极区域设置在半导体层中。 在两个相邻的堆叠结构之间设置至少一个公共源区。 所述至少一个公共源区域沿第一方向延伸。 第一导电类型的阱拾取区域设置在半导体层中。 至少一个阱拾取区域与至少一个堆叠结构的两端相邻。

公开(公告)号：US20140140140A1

公开(公告)日：2014-05-22

申请号：US14164586

申请日：2014-01-27

申请人： Jaesung Sim ,  Jungdal Choi

发明人： Jaesung Sim ,  Jungdal Choi

IPC分类号： G11C16/34

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/3418

摘要： Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).

摘要翻译： 集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。 提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。 擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

公开(公告)号：US20120170375A1

公开(公告)日：2012-07-05

申请号：US13342361

申请日：2012-01-03

申请人： Jaesung Sim ,  Jungdal Choi

发明人： Jaesung Sim ,  Jungdal Choi

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/3418

摘要： Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).

摘要翻译： 集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。 提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。 擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

公开(公告)号：US07813183B2

公开(公告)日：2010-10-12

申请号：US12119060

申请日：2008-05-12

申请人： Seunghyun Moon ,  Kihwan Choi ,  Jaesung Sim ,  Jungdal Choi

发明人： Seunghyun Moon ,  Kihwan Choi ,  Jaesung Sim ,  Jungdal Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/3404

摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.

摘要翻译： 编程或擦除具有电荷存储层的非易失性存储器件的方法包括执行至少一个单元编程或擦除循环，每个单元编程或擦除循环包括应用编程脉冲，擦除脉冲，时间延迟，软擦除脉冲， 软编程脉冲和/或验证脉冲作为对非易失性存储器件的一部分（例如，字线或衬底）的正或负电压。

公开(公告)号：US20080291737A1

公开(公告)日：2008-11-27

申请号：US12119060

申请日：2008-05-12

申请人： Seunghyun MOON ,  Kihwan CHOI ,  Jaesung SIM ,  Jungdal CHOI

发明人： Seunghyun MOON ,  Kihwan CHOI ,  Jaesung SIM ,  Jungdal CHOI

IPC分类号： G11C16/06

CPC分类号： G11C16/3404

摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.

摘要翻译： 编程或擦除具有电荷存储层的非易失性存储器件的方法包括执行至少一个单元编程或擦除循环，每个单元编程或擦除循环包括应用编程脉冲，擦除脉冲，时间延迟，软擦除脉冲， 软编程脉冲和/或验证脉冲作为对非易失性存储器件的一部分（例如，字线或衬底）的正或负电压。

公开(公告)号：US11089829B2

公开(公告)日：2021-08-17

申请号：US16287360

申请日：2019-02-27

申请人： Jaesung Sim

发明人： Jaesung Sim

IPC分类号： A41G5/00

摘要： A head covering with a band portion in a shape of a flat strip or loop and a plurality of flat members that are connected to or a part of the band is disclosed. The flat members projects toward a top side of the band. An outer surface of the flat members includes or is made of a material that can be fastened to a certain corresponding type of material. Thereby, the invention provides a foundation for hairpieces having a fastening component that corresponds to a fastening component used in the invention. The flat members as a whole generally cover a scalp of a head but not completely, exposing the scalp through gaps between flat members. Especially, a top portion or a crown of a scalp is generally exposed due to an open-top construction of the head covering. However, as a single hairpiece is fastened to multiple flat members, the hairpiece in turn works to hold the multiple flat members together. When more hairpieces are attached to flat members, the flat members become structurally solid in a shape that conforms to the contour of the scalp. In so doing, hairpieces cover and bridge the gaps between flat members, thereby completely covering a head.

公开(公告)号：US20200268084A1

公开(公告)日：2020-08-27

申请号：US16287360

申请日：2019-02-27

申请人： Jaesung SIM

发明人： Jaesung SIM

IPC分类号： A41G5/00

摘要： A head covering with a band portion in a shape of a flat strip or loop and a plurality of flat members that are connected to or a part of the band is disclosed. The flat members projects toward a top side of the band. An outer surface of the flat members includes or is made of a material that can be fastened to a certain corresponding type of material. Thereby, the invention provides a foundation for hairpieces having a fastening component that corresponds to a fastening component used in the invention. The flat members as a whole generally cover a scalp of a head but not completely, exposing the scalp through gaps between flat members. Especially, a top portion or a crown of a scalp is generally exposed due to an open-top construction of the head covering. However, as a single hairpiece is fastened to multiple flat members, the hairpiece in turn works to hold the multiple flat members together. When more hairpieces are attached to flat members, the flat members become structurally solid in a shape that conforms to the contour of the scalp. In so doing, hairpieces cover and bridge the gaps between flat members, thereby completely covering a head.

公开(公告)号：US08462558B2

公开(公告)日：2013-06-11

申请号：US12805500

申请日：2010-08-03

申请人： Seunghyun Moon ,  Kihwan Choi ,  Jaesung Sim ,  Jungdal Choi

发明人： Seunghyun Moon ,  Kihwan Choi ,  Jaesung Sim ,  Jungdal Choi

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/3404

摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.

摘要翻译： 编程或擦除具有电荷存储层的非易失性存储器件的方法包括执行至少一个单元编程或擦除循环，每个单元编程或擦除循环包括应用编程脉冲，擦除脉冲，时间延迟，软擦除脉冲， 软编程脉冲和/或验证脉冲作为对非易失性存储器件的一部分（例如，字线或衬底）的正或负电压。