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1.发明授权System and apparatus for managing latency-sensitive interaction in virtual environments 有权用于管理虚拟环境中的延迟敏感交互的系统和设备公开(公告)号：US07925485B2
公开(公告)日：2011-04-12
申请号：US11552709
申请日：2006-10-25
CPC分类号： A63F13/355 , A63F13/12 , A63F13/358 , A63F13/57 , A63F2300/534 , A63F2300/538 , A63F2300/5533 , A63F2300/64 , A63F2300/8017
摘要： A structure and method comprises a data structure representing a characteristic of an object in the virtual interactive environment. The device further comprises a client simulator to perform a first simulation of the characteristic of the object in the virtual interactive environment and a server simulator to perform a second simulation of the characteristic of the object in the virtual interactive environment. The device further comprises a synchronizer to synchronize the first and the second simulations.
摘要翻译： 一种结构和方法包括表示虚拟交互环境中的对象的特征的数据结构。 该设备还包括客户端模拟器，以在虚拟交互环境中执行对象的特性的第一模拟，以及服务器模拟器，以在虚拟交互环境中执行对象的特征的第二模拟。 该装置还包括同步器以同步第一和第二模拟。
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公开(公告)号：US20080104223A1
公开(公告)日：2008-05-01
申请号：US11553000
申请日：2006-10-26
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L67/34 , G06F9/5044 , H04L67/10
摘要： A system and method for accelerating the execution of applications in computing environments. The method includes receiving a request for execution of a plug-in of a computing application and analyzing a network for accelerators for executing the plug-in. The method further includes identifying a designated accelerator residing on a device that is remote from the application and executing the plug-in with the designated accelerator.
摘要翻译： 一种用于加速计算环境中应用程序执行的系统和方法。 该方法包括接收执行计算应用的插件的请求，并分析用于执行插件的加速器的网络。 该方法还包括识别驻留在远离应用的设备上的指定加速器并且使用指定的加速器来执行插件。
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公开(公告)号：US08838674B2
公开(公告)日：2014-09-16
申请号：US11553000
申请日：2006-10-26
CPC分类号： H04L67/34 , G06F9/5044 , H04L67/10
摘要： A system and method for accelerating the execution of applications in computing environments. The method includes receiving a request for execution of a plug-in of a computing application and analyzing a network for accelerators for executing the plug-in. The method further includes identifying a designated accelerator residing on a device that is remote from the application and executing the plug-in with the designated accelerator.
摘要翻译： 一种用于加速计算环境中应用程序执行的系统和方法。 该方法包括接收执行计算应用的插件的请求，并分析用于执行插件的加速器的网络。 该方法还包括识别驻留在远离应用的设备上的指定加速器并且使用指定的加速器来执行插件。
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4.发明申请SYSTEM AND APPARATUS FOR MANAGING LATENCY-SENSITIVE INTERACTION IN VIRTUAL ENVIRONMENTS 有权管理虚拟环境中的敏感互动的系统和装置公开(公告)号：US20080102955A1
公开(公告)日：2008-05-01
申请号：US11552709
申请日：2006-10-25
IPC分类号： A63F9/24
CPC分类号： A63F13/355 , A63F13/12 , A63F13/358 , A63F13/57 , A63F2300/534 , A63F2300/538 , A63F2300/5533 , A63F2300/64 , A63F2300/8017
摘要： A structure and method comprises a data structure representing a characteristic of an object in the virtual interactive environment. The device further comprises a client simulator to perform a first simulation of the characteristic of the object in the virtual interactive environment and a server simulator to perform a second simulation of the characteristic of the object in the virtual interactive environment. The device further comprises a synchronizer to synchronize the first and the second simulations.
摘要翻译： 一种结构和方法包括表示虚拟交互环境中的对象的特征的数据结构。 该设备还包括客户端模拟器，以在虚拟交互环境中执行对象的特性的第一模拟，以及服务器模拟器，以在虚拟交互环境中执行对象的特征的第二模拟。 该装置还包括同步器以同步第一和第二模拟。
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5.发明申请SYSTEM AND METHOD FOR LOAD BALANCING DISTRIBUTED SIMULATIONS IN VIRTUAL ENVIRONMENTS 审中-公开虚拟环境中负载平衡分布式仿真的系统与方法公开(公告)号：US20080104609A1
公开(公告)日：2008-05-01
申请号：US11553178
申请日：2006-10-26
IPC分类号： G06F9/46
摘要： A device comprises two or more nodes for processing a simulation of a virtual interactive environment. The two or more nodes comprising at least one component to determine workload amongst at least a first node and a second node the two or more nodes. The at least one component further delegates work to the second node when the workload on the first node exceeds a predetermined boundary, and accepts work from the second node when the workload on the second node is within the predetermined boundary.
摘要翻译： 一种设备包括用于处理虚拟交互环境的仿真的两个或多个节点。 所述两个或多个节点包括至少一个组件以确定至少第一节点和第二节点之间的两个或更多节点的工作负载。 当第一节点上的工作负载超过预定边界时，至少一个组件进一步将工作委托给第二节点，并且当第二节点上的工作负载在预定边界内时，从第二节点接受工作。
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6.发明授权Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache 失效使用组合回写队列和受害缓存的微处理器电路，系统和方法
公开(公告)号：US6038645A
公开(公告)日：2000-03-14
申请号：US919732
申请日：1997-08-28
IPC分类号： G06F12/08
CPC分类号： G06F12/0804
摘要： A microprocessor (10) comprising a central processor unit core (12) operable to write information during a write cycle and a cache circuit (18) coupled to the central processor unit core and operable to evict information. The microprocessor further includes a combined storage queue (16) coupled to the central processor unit core and to the cache circuit. The combined storage queue includes a set of logical storage blocks (22c) which is operable to store both information written by the central processor unit core and information evicted by the cache circuit. Other circuits, systems, and methods are also disclosed and claimed.
摘要翻译： 一种微处理器（10），包括可操作以在写入周期期间写入信息的中央处理器单元核心（12）和耦合到所述中央处理器单元核心并可操作以驱逐信息的高速缓存电路（18）。 微处理器还包括耦合到中央处理器单元核心和高速缓存电路的组合存储队列（16）。 组合的存储队列包括一组逻辑存储块（22c），其可操作以存储由中央处理器单元核心写入的信息和由高速缓存电路驱逐的信息。 还公开并要求保护其他电路，系统和方法。
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7.发明授权Pipelined microprocessor with branch misprediction cache circuits, systems and methods 失效流水线微处理器具有分支错误预测缓存电路，系统和方法
公开(公告)号：US5881277A
公开(公告)日：1999-03-09
申请号：US874786
申请日：1997-06-13
申请人： James O. Bondi , Simonjit Dutta , Ashwini K. Nanda
发明人： James O. Bondi , Simonjit Dutta , Ashwini K. Nanda
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/3804 , G06F9/3842
摘要： A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit. The output of the multiplexer is coupled to an input of a second stage (50) of the intermediary stages, wherein the second stage follows the first stage. Other circuits, systems, and methods are also disclosed and claimed.
摘要翻译： 一种微处理器，包括包括多个连续指令级的指令流水线（36）。 指令通过多个中间级（40至52）和多个连续指令级的结束级（54）从初始阶段（38）传递。 微处理器还包括一个存储电路（58），它被耦合以接收从中间级的第一级（48）输出的程序线程信息。 此外，微处理器包括选择电路（56），其包括第一输入端，第二输入端和用于从其第一和第二输入端输出输出信号的输出端。 选择电路的第一输入被耦合以接收从第一级输出的输出信息。 选择电路的第二输入被耦合以接收从存储电路输出的程序线程信息。 多路复用器的输出耦合到中间级的第二级（50）的输入端，其中第二级跟随第一级。 还公开并要求保护其他电路，系统和方法。
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公开(公告)号：US07624222B2
公开(公告)日：2009-11-24
申请号：US11539211
申请日：2006-10-06
CPC分类号： G06F13/4031 , G06F13/1657
摘要： A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.
摘要翻译： 一种包括南桥，连接到南桥的第一处理器和连接到南桥的第二处理器的系统。 该系统还包括连接到南桥的至少一个设备和耦合到南桥的资源管理器，其分配在第一处理器和第二处理器之间的至少一个设备的使用。
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公开(公告)号：US20080086583A1
公开(公告)日：2008-04-10
申请号：US11539211
申请日：2006-10-06
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F13/1657
摘要： A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.
摘要翻译： 一种包括南桥，连接到南桥的第一处理器和连接到南桥的第二处理器的系统。 该系统还包括连接到南桥的至少一个设备和耦合到南桥的资源管理器，其分配在第一处理器和第二处理器之间的至少一个设备的使用。
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10.发明授权Microprocessor system with burstable, non-cacheable memory access support 失效微处理器系统具有可突发，不可缓存的内存访问支持
公开(公告)号：US06032225A
公开(公告)日：2000-02-29
申请号：US769194
申请日：1996-12-18
CPC分类号： G06F13/28 , G06F12/0888
摘要： A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected. According to a second embodiment of the invention, burst access to non-cacheable memory space (32) is acknowledged by the memory controller (60) by way of a burst acknowledge signal (BEN#) that is separate from the cache acknowledgment signal (KEN#).
摘要翻译： 基于x86架构的微处理器（5）公开了一种基于微处理器的系统（2）。 该系统包括存储器地址空间（30）和输入/输出地址空间（40），其中以I / O映射方式执行输入/输出操作。 根据本发明的第一实施例，微处理器（5）结合控制信号来确定高速缓存请求信号（CACHE＃），对主存储器（32）的被高速缓存访问阻止的区域执行突发存取 （M / IO＃），表示请求I / O操作。 存储器控制器（10）将该组合解释为对非可缓存存储器位置（32）的突发请求，指示通过断言高速缓存确认控制信号（KEN＃）来准许突发存取，然后实现突发存储器访问 。 根据本发明的第二实施例，通过与高速缓存确认信号（KEN）分离的突发确认信号（BEN＃），由存储器控制器（60）确认对非可缓存存储器空间（32）的突发访问 ＃）。
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