公开(公告)号：US20170179088A1

公开(公告)日：2017-06-22

申请号：US15449510

申请日：2017-03-03

Applicant: CREE, INC.

Inventor： Bernd Keller ,  Ashay Chitnis ,  Nicholas W. Medendorp, JR. ,  James Ibbetson ,  Max Batres

IPC: H01L25/075 ,  H01L33/50 ,  H01L33/38 ,  H01L33/08 ,  H01L33/62

CPC classification number: H01L25/0756 ,  H01L33/08 ,  H01L33/22 ,  H01L33/385 ,  H01L33/46 ,  H01L33/486 ,  H01L33/50 ,  H01L33/505 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/49107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.

公开(公告)号：US10199360B2

公开(公告)日：2019-02-05

申请号：US15449510

申请日：2017-03-03

Applicant: CREE, INC.

Inventor： Bernd Keller ,  Ashay Chitnis ,  Nicholas W. Medendorp, Jr. ,  James Ibbetson ,  Max Batres

IPC: H01L33/00 ,  H01L25/075 ,  H01L33/58 ,  H01L33/50 ,  H01L33/38 ,  H01L33/62 ,  H01L33/08 ,  H01L33/22 ,  H01L33/48 ,  H01L33/46

Abstract: A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.

公开(公告)号：US20150008457A1

公开(公告)日：2015-01-08

申请号：US14494795

申请日：2014-09-24

Applicant: CREE, INC.

Inventor： Ashay Chitnis ,  James Ibbetson ,  Bernd Keller

IPC: H01L33/44 ,  H01L33/62 ,  H01L33/50 ,  H01L33/10 ,  H01L33/08 ,  H01L27/15

CPC classification number: H01L33/44 ,  H01L27/15 ,  H01L33/08 ,  H01L33/10 ,  H01L33/502 ,  H01L33/505 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/13 ,  H01L2933/0041 ,  H01L2933/0066

Abstract: Methods for fabricating light emitting diode (LED) chips one of which comprises flip-chip mounting a plurality of LEDs on a surface of a submount wafer and forming a coating over said LEDs. The coating comprising a conversion material at least partially covering the LEDs. The coating is planarized to the desired thickness with the coating being continuous and unobstructed on the top surface of the LEDs. The LEDs chips are then singulated from the submount wafer. An LED chip comprising a lateral geometry LED having first and second contacts, with the LED flip-chip mounted to a submount by a conductive bonding material. A phosphor loaded binder coats and at least partially covers the LED. The binder provides a substantially continuous and unobstructed coating over the LED. The phosphor within the coating absorbs and converts the wavelength of at least some of the LED light with the coating planarized to achieve the desired emission color point of the LED chip.

Abstract translation: 制造发光二极管（LED）芯片的方法，其中之一包括倒装芯片，将多个LED安装在底座晶片的表面上并在所述LED上形成涂层。 所述涂层包含至少部分地覆盖所述LED的转化材料。 将涂层平坦化到所需的厚度，涂层在LED的顶表面上是连续的并且不受阻碍。 然后将LED芯片从底座晶片分离。 一种LED芯片，包括具有第一和第二触点的侧向几何形状LED，其中LED倒装芯片通过导电接合材料安装到基座。 荧光体负载的粘合剂涂层并且至少部分地覆盖LED。 粘合剂在LED上提供基本上连续且无障碍的涂层。 涂层内的荧光体吸收并转换至少一些LED光的波长，使涂层平坦化，以达到LED芯片的期望的发射色点。