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公开(公告)号：US11188700B2
公开(公告)日：2021-11-30
申请号：US17053550
申请日：2019-08-15
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Nan Zhang , Jing Zhou , Hao Wang , Zhan Gao , Maoqian Zhu , Cheng Zhou , Zhijin Li , Lin Wu , Shuming Guo , Yong Huang
IPC: G06F30/367 , G06F30/392 , G06F119/06
Abstract: The present application relates to a resistance simulation method for a power device, comprising: establishing an equivalent resistance model of a power device, wherein the connection relationship of N fingers is equivalent to N resistors Rb connected in parallel, input ends of adjacent resistors Rb are connected by means of a resistor Ra, output ends of adjacent resistors Rb are connected by means of a resistor Rc, R a = 1 N R 0 , R c = 1 N R 1 , and Rb=RDEV*N+RS+RD, wherein R0 and R1 are respectively resistances of a source metal strip and a drain metal strip, Rs is a metal resistor of a first intermediate layer connecting one source region to the source metal strip, RD is a metal resistor of a second intermediate layer connecting one drain region to the drain metal strip, and RDEV is the channel resistance of the power device; and calculating the resistance of the equivalent resistance model as the resistance of the power device.
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Patent Agency Ranking
公开(公告)号：US11557959B2
公开(公告)日：2023-01-17
申请号：US16959015
申请日：2018-12-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
Inventor： Shen Xu , Minggang Chen , Hao Wang , Jinyu Xiao , Wei Su , Weifeng Sun , Longxing Shi
Abstract: An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.
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公开(公告)号：US11711088B2
公开(公告)日：2023-07-25
申请号：US17419548
申请日：2019-12-23
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
CPC classification number: H03M1/002 , H03M1/0624
Abstract: An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.
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公开(公告)号：US12165714B2
公开(公告)日：2024-12-10
申请号：US17916927
申请日：2021-04-28
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Bin Chen , Youhui Li , Ming Gu , Xinmiao Zhao , Hao Wang , Shuming Guo , Zongchuan Wang , Nan Zhang
Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.
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5.发明授权公开(公告)号：US11323039B2
公开(公告)日：2022-05-03
申请号：US16959001
申请日：2018-12-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
Inventor： Weifeng Sun , Rongrong Tao , Hao Wang , Jinyu Xiao , Wei Su , Shen Xu , Longxing Shi
Abstract: A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a critical value Tset, calculating a time interval Ttap between adjacent zero points in the current connection time, outputting a shutdown signal at the zero points, and comparing the time interval Ttap with the preset critical value Tset; when Ttap>Tset, controlling the current shutdown time to be less than the shutdown time of the preceding cycle and outputting a start signal; when Ttap=0, controlling the current shutdown time to be greater than the shutdown time of the preceding cycle and outputting a start signal; and when 0
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公开(公告)号：US11201557B2
公开(公告)日：2021-12-14
申请号：US16959116
申请日：2018-12-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
Inventor： Qinsong Qian , Shengyou Xu , Feng Lin , Hao Wang , Wei Su , Qi Liu , Longxing Shi
Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.
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