公开(公告)号：US08551829B2

公开(公告)日：2013-10-08

申请号：US12943015

申请日：2010-11-10

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/70

CPC分类号： H01L29/66795

摘要： A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.

摘要翻译： 一种制造多栅极晶体管器件的方法包括：提供其上形成有第一图案化半导体层的半导体衬底，顺序地形成栅极电介质层和覆盖半导体衬底上的第一图案化半导体层的一部分的栅极层， 以形成第二图案化半导体层，并且执行选择性外延生长工艺以在第二图案化半导体层的表面上形成外延层。

公开(公告)号：US20130193585A1

公开(公告)日：2013-08-01

申请号：US13363390

申请日：2012-02-01

申请人： Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

发明人： Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

IPC分类号： H01L23/48 ,  H01L21/302

CPC分类号： H01L21/3085 ,  H01L21/3086 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

公开(公告)号：US20130078780A1

公开(公告)日：2013-03-28

申请号：US13241188

申请日：2011-09-22

申请人： Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

发明人： Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28229 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.

摘要翻译： 半导体工艺包括以下步骤。 在基板上形成中间层。 在中间层上形成第一金属氧化物层。 进行还原处理以将第一金属氧化物层还原成金属层。 执行高温处理以将金属层转变为第二金属氧化物层。

公开(公告)号：US08361854B2

公开(公告)日：2013-01-29

申请号：US13052338

申请日：2011-03-21

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC分类号： H01L21/8238

CPC分类号： H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

摘要： A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.

摘要翻译： 鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。 高k金属栅极形成在基板和鳍状通道上。 制造鳍式场效应晶体管结构的工艺包括以下步骤。 首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。 通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。 在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。 然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。

公开(公告)号：US20120322260A1

公开(公告)日：2012-12-20

申请号：US13161849

申请日：2011-06-16

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC分类号： H01L21/283

CPC分类号： H01L21/76898 ,  H01L21/76883

摘要： A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.

摘要翻译： 通硅通孔形成方法包括以下步骤。 首先，提供半导体衬底。 然后，在半导体衬底中形成贯通硅通孔导体，并且使贯通硅通孔导体的上侧与半导体衬底的表面处于相同的水平。 然后，去除一部分通硅导通导体，使贯通硅通孔导体的顶面位于比半导体衬底的表面低的水平面上， 硅通孔导体。

公开(公告)号：US20120196410A1

公开(公告)日：2012-08-02

申请号：US13017534

申请日：2011-01-31

申请人： Teng-Chun TSAI ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chin-Cheng Chien

发明人： Teng-Chun TSAI ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chin-Cheng Chien

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/66545

摘要： A method for fabricating a fin-FET, wherein the method comprises several steps as follows: A substrate is first provided, and a silicon fin is then formed in the substrate. Next a dielectric layer is formed on the silicon fin and the substrate. A poly silicon layer is subsequently formed on the dielectric layer, and the poly silicon layer is then planarized. Subsequently, a poly silicon gate is formed and a portion of the silicon fin is exposed by patterning the planarized poly silicon layer. A source and a drain are separately formed on two opposite sides of the exposed silicon fin adjacent to the poly silicon gate.

摘要翻译： 一种制造鳍式FET的方法，其中该方法包括以下几个步骤：首先提供衬底，然后在衬底中形成硅片。 接下来，在硅片和衬底上形成介电层。 随后在电介质层上形成多晶硅层，然后将多晶硅层平坦化。 随后，通过对平坦化的多晶硅层进行构图，形成多晶硅栅极并且使硅片的一部分露出。 源极和漏极分别形成在与多晶硅栅极相邻的暴露的硅鳍片的两个相对侧上。

公开(公告)号：US20120115284A1

公开(公告)日：2012-05-10

申请号：US12943015

申请日：2010-11-10

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/336

CPC分类号： H01L29/66795

摘要： A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.

摘要翻译： 一种制造多栅极晶体管器件的方法包括：提供其上形成有第一图案化半导体层的半导体衬底，顺序地形成栅极电介质层和覆盖半导体衬底上的第一图案化半导体层的一部分的栅极层， 以形成第二图案化半导体层，并且执行选择性外延生长工艺以在第二图案化半导体层的表面上形成外延层。

公开(公告)号：US08822284B2

公开(公告)日：2014-09-02

申请号：US13370231

申请日：2012-02-09

申请人： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

发明人： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/318 ,  H01L21/314

CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

摘要： A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

摘要翻译： 描述了制造FinFET的方法。 图案化半导体衬底以形成奇数鳍片。 间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。 然后在间隔件之间的基板上均匀形成翅片。 还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

公开(公告)号：US08647941B2

公开(公告)日：2014-02-11

申请号：US13211319

申请日：2011-08-17

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/8238

CPC分类号： H01L29/7846 ,  H01L21/76283 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.

摘要翻译： 形成半导体器件的方法包括以下步骤。 提供具有第一应变硅层的半导体衬底。 然后，形成诸如浅沟槽隔离（STI）的绝缘区域，其中绝缘区域的深度基本上大于第一应变硅层的深度。 随后，去除第一应变硅层，形成第二应变硅层以代替第一应变硅层。

公开(公告)号：US08497198B2

公开(公告)日：2013-07-30

申请号：US13243485

申请日：2011-09-23

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/66795

摘要： A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.

摘要翻译： 半导体工艺描述如下。 在基板上形成多个虚设图案。 在基板上共形形成掩模材料层，以覆盖虚设图案。 掩模材料层具有与虚拟图案不同的蚀刻速率。 除去掩模材料层的一部分，以便在每个虚设图案的各个侧壁上形成掩模层。 掩模层的上表面和每个虚拟图案的上表面基本上共面。 虚拟图案被去除。 使用掩模层作为掩模去除衬底的一部分，以便形成多个翅片结构和交替布置在衬底中的多个沟槽。 去除掩模层。