摘要:
Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.
摘要:
An enable propagation controller employed in an integrated circuit operates in either a sequence manager mode or a transparent mode. When operating in the sequence manager mode, the enable propagation controller allows a set of signals intended to enable either a set of transmission or a set of reception signals to pass through to their corresponding transmission or receptions sub-circuits. Each of the signals in the desired set is allowed to pass through in a predetermined sequence and for a predetermined duration that may or may not be influenced by a set of control bits received by the enable propagation controller. When operating in a transparent mode, all enable signals are allowed to pass through to corresponding intended sub-circuits.
摘要:
Interdigitation and surface mounting of a block filter that has at least a first resonator and that has at least a first pole and at least a first zero in its transfer function provides a surface mountable block filter having selectable frequency rejection response operation.
摘要:
A dual-port voltage control oscillator for use in a frequency synthesizer has first and second input ports and an output. The first port is coupled in a phase-locked-loop configuration for receiving input data and a reference frequency. The phase-locked-loop tunes the oscillator in response to a channel selection and trim parameter. The second port of the oscillator has a variable gain characteristic. A multiplier is coupled to the second port for multiplying the input data by a transfer function to alter the input data thereby compensating for the second port variable gain characteristic.