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公开(公告)号：US20170272044A1
公开(公告)日：2017-09-21
申请号：US15270687
申请日：2016-09-20
Inventor： John L. MELANSON , Eric J. KING , Zhaohui HE , Siddharth MARU
CPC classification number: H03F3/2173 , H03F3/187 , H03F2200/165 , H03F2200/432 , H04R3/02 , H04R2420/03
Abstract: A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input.
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公开(公告)号：US20230344394A1
公开(公告)日：2023-10-26
申请号：US18303750
申请日：2023-04-20
Inventor： John L. MELANSON , Abhishek MUKHERJEE , Lingli ZHANG , Zhaohui HE
CPC classification number: H03F3/2175 , H03F1/3264 , H03F1/0255 , H03F2200/351 , H03F2200/03
Abstract: A system may include an analog loop filter comprising a plurality of analog integrators, the analog loop filter configured to receive an analog signal input and a feedback output signal, at least one sampler for sampling outputs of the analog integrators, a second loop filter coupled between an output of an analog pulse-width modulation driver and a digital pulse-width modulation controller, wherein the second loop filter comprises at least one integrator and is configured to receive sampled outputs of the analog integrators from the at least one sampler and receive a feedback pulse-width modulation signal from the analog pulse-width modulation driver, and a correction subsystem configured to apply a non-linear function to a signal path of the second loop filter in order to compensate for non-linearity introduced as a result of sampling outputs of the analog integrators.
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Patent Agency Ranking
公开(公告)号：US20170271996A1
公开(公告)日：2017-09-21
申请号：US15282790
申请日：2016-09-30
Inventor： Eric J. KING , Zhaohui HE , Siddharth MARU , John L. MELANSON
IPC: H02M5/293
CPC classification number: H03F3/2171 , H02M5/293 , H02M2005/2932 , H03F1/0216 , H03F1/0227 , H03F1/32 , H03F3/185 , H03F3/2173 , H03F3/2178 , H03F2200/03 , H03F2200/153 , H03F2200/432 , H04R3/12
Abstract: A method may include controlling switches of a switching full-bridge of a signal processing system to commutate polarity of a capacitor with respect to the first processing path output and a second processing path output of the signal processing system in response to a condition for commutating connectivity of the switching full-bridge and inserting a feedforward compensation that bypasses a loop filter of the second processing path in order to prevent discontinuities caused by commutating polarity of the capacitor from being compensated by the loop filter.
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公开(公告)号：US20170207759A1
公开(公告)日：2017-07-20
申请号：US15270631
申请日：2016-09-20
Inventor： Zhaohui HE , Eric J. KING , Siddharth MARU , John L. MELANSON
CPC classification number: H03F3/217 , H03F1/04 , H03F1/34 , H03F3/185 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/351 , H03F2200/432 , H03F2203/45034 , H04R3/12 , H04R2420/03
Abstract: A switching power stage for producing a load voltage may include a first processing path having a first output, a second processing path having a second output, a first plurality of switches comprising at least a first switch coupled between the first output and a first load terminal and a second switch coupled between the first output and the second load terminal, a second plurality of switches comprising at least a third switch coupled between the second output and the first load terminal and a fourth switch coupled between the second output and the second load terminal, and a controller configured to control switches in order to generate the load voltage as a function of an input signal such that one of the first switch and the second switch operates in a linear region of operation and one of the third switch and the fourth switch operates in a saturated region of operation for a predominance of a dynamic rage of the load voltage.
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公开(公告)号：US20170207755A1
公开(公告)日：2017-07-20
申请号：US15168680
申请日：2016-05-31
Inventor： Zhaohui HE , Eric J. KING , Siddharth MARU , John L. MELANSON
CPC classification number: H03F1/32 , H03F1/0211 , H03F1/0227 , H03F1/0244 , H03F3/183 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/45076 , H03F2200/03 , H03F2203/45034 , H04R3/00 , H04R2420/03
Abstract: A switching power stage for producing a load voltage at a load output of the switching power stage, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first and the second load voltages, that may include: a power converter comprising a power inductor and a plurality of switches, wherein the power converter is configured to drive a power converter output terminal; a linear amplifier configured to drive a linear amplifier output terminal; and a controller for controlling the plurality of switches and the linear amplifier in order to generate the load voltage as a function of an input signal to the controller such that energy delivered to the load output is supplied predominantly by the power converter.
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公开(公告)号：US20230122151A1
公开(公告)日：2023-04-20
申请号：US17848550
申请日：2022-06-24
Inventor： Zhaohui HE , Neel PRAMANIK , Lingli ZHANG , Wei XU , Prashanth DRAKSHAPALLI
IPC: H03F3/45
Abstract: A method for calibrating a fully-differential input system may include determining a first voltage of a first node of the fully-differential input system, wherein the first node is coupled at the first node to a plurality of first resistors in a first star configuration, determining a second voltage of a second node of the fully-differential input system, wherein the second node is coupled at the second node to a plurality of second resistors in a second star configuration, each resistor of the plurality of second resistors corresponding to a respective resistor of the plurality of first resistors, and trimming individual resistances of the plurality of first resistors and the plurality of second resistors in order to maintain a difference of a first voltage at the first node and a second voltage of the second node at approximately zero.
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公开(公告)号：US20220376618A1
公开(公告)日：2022-11-24
申请号：US17678527
申请日：2022-02-23
Inventor： Yongjie CHENG , Lingli ZHANG , John L. MELANSON , Thomas H. HOFF , Eric J. KING , Zhaohui HE
Abstract: This application relates to methods and apparatus for driving a transducer. A transducer driver has a switch network is operable to selectively connect a driver output to any of a first set of at least three different switching voltages. which are, in use, maintained throughout a switching cycle of the driver apparatus. The switch network is also operable to selectively connect the driver output to flying capacitor driver. A controller is configured to control the switch network and flying capacitor driver to generate a drive signal at the driver output based on an input signal, wherein in one mode of operation the driver output is switched between two of the first set of switching voltages with a controlled duty cycle and in another mode of operation the driver output is connected to the flying capacitor driver which is switched between first and second states with a controlled duty cycle.
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