公开(公告)号：US09678669B2

公开(公告)日：2017-06-13

申请号：US14083437

申请日：2013-11-18

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

IPC: G06F17/50 ,  G06F9/455 ,  G06F3/06 ,  G06F12/0844 ,  G06F12/0846 ,  G06F12/0855

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/0844 ,  G06F12/0851 ,  G06F12/0855

Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

公开(公告)号：US09520178B2

公开(公告)日：2016-12-13

申请号：US14831008

申请日：2015-08-20

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell.

Abstract translation: 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。 为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。

公开(公告)号：US09147466B2

公开(公告)日：2015-09-29

申请号：US14274518

申请日：2014-05-09

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

Abstract translation: 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。 为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。 因此，具有电压辅助的空间域复用允许单端写入来处理在单个周期中处理的两个独立的写操作。 可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

公开(公告)号：US20160179394A1

公开(公告)日：2016-06-23

申请号：US14083437

申请日：2013-11-18

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/0844 ,  G06F12/0851 ,  G06F12/0855

Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

Abstract translation: 为集成电路设计存储器子系统可能是耗时且昂贵的任务。 为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。 自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。 潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。 满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。 当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及用于存储器系统的测试套件。

公开(公告)号：US09965211B2

公开(公告)日：2018-05-08

申请号：US15259602

申请日：2016-09-08

Applicant: Cisco Technology, Inc.

Inventor： Sharad Vasantrao Chole ,  Shang-Tse Chuang ,  Georges Akis ,  Felice Bonardi ,  Rong Pan

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/1045 ,  G06F12/127 ,  G06F12/06

CPC classification number: H04L47/00 ,  G06F12/0623 ,  G06F12/0692 ,  G06F12/1045 ,  G06F12/127

Abstract: Provided are a method, a non-transitory computer-readable storage device and an apparatus for managing use of a shared memory buffer that is partitioned into multiple banks and that stores incoming data received at multiple inputs in accordance with a multi-slice architecture. A particular bank is allocated to a corresponding slice. Received respective data packets are associated with corresponding slices based on which respective inputs they are received. Determine, based on a state of the shared memory buffer, to transfer contents of all occupied cells of the particular bank. Writes to the bank are stopped, contents of occupied cells are transferred to cells of one or more other banks associated with the particular bank's slice, information is stored indicating where the contents have been transferred, and the particular bank is returned to a shared pool after transferring is completed.

公开(公告)号：US20180067683A1

公开(公告)日：2018-03-08

申请号：US15259602

申请日：2016-09-08

Applicant: Cisco Technology, Inc.

Inventor： Sharad Vasantrao Chole ,  Shang-Tse Chuang ,  Georges Akis ,  Felice Bonardi ,  Rong Pan

IPC: G06F3/06

CPC classification number: H04L47/00 ,  G06F12/0623 ,  G06F12/0692 ,  G06F12/1045 ,  G06F12/127

Abstract: Provided are a method, a non-transitory computer-readable storage device and an apparatus for managing use of a shared memory buffer that is partitioned into multiple banks and that stores incoming data received at multiple inputs in accordance with a multi-slice architecture. A particular bank is allocated to a corresponding slice. Received respective data packets are associated with corresponding slices based on which respective inputs they are received. Determine, based on a state of the shared memory buffer, to transfer contents of all occupied cells of the particular bank. Writes to the bank are stopped, contents of occupied cells are transferred to cells of one or more other banks associated with the particular bank's slice, information is stored indicating where the contents have been transferred, and the particular bank is returned to a shared pool after transferring is completed.

公开(公告)号：US10042573B2

公开(公告)日：2018-08-07

申请号：US15213492

申请日：2016-07-19

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/08

Abstract: A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

公开(公告)号：US20160328170A1

公开(公告)日：2016-11-10

申请号：US15213492

申请日：2016-07-19

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0673 ,  G06F12/08 ,  G06F2212/254

Abstract: A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

Abstract translation: 公开了一种用于设计和构造分层存储器系统的系统和方法。 公开了多种不同的算法存储器块。 每个算法存储器块包括实现特定存储算法和一组较低级存储器组件的存储器控​​制器。 这些较低级存储器组件中的每一个可以用另一个算法存储器块或基本存储器块来构造。 通过在各种不同的分层组织中组织算法存储器块，可以创建提供新特征的不同复杂的存储器系统。

公开(公告)号：US20150339227A1

公开(公告)日：2015-11-26

申请号：US14730696

申请日：2015-06-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0292 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/657

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. This allows the memory system to both store and read data in the same cycle with no conflicts.

Abstract translation: 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。 这允许存储器系统在相同周期内存储和读取数据，而不会发生冲突。

公开(公告)号：US09390212B2

公开(公告)日：2016-07-12

申请号：US14702971

申请日：2015-05-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC: G11C11/00 ,  G06F17/50 ,  G11C11/419

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.