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公开(公告)号：US09881256B2
公开(公告)日：2018-01-30
申请号：US15505522
申请日：2015-08-21
Applicant: D-Wave Systems Inc.
Inventor： Firas Hamze , Andrew Douglas King , Jack Raymond , Aidan Patrick Roy , Robert Israel , Evgeny Andriyash , Catherine McGeoch , Mani Ranjbar
CPC classification number: G06N99/002 , G06F9/02 , G06F9/32 , G06F15/18 , G06F15/76 , G06F17/10 , G06N3/12
Abstract: Computational systems implement problem solving using heuristic solvers or optimizers. Such may iteratively evaluate a result of processing, and modify the problem or representation thereof before repeating processing on the modified problem, until a termination condition is reached. Heuristic solvers or optimizers may execute on one or more digital processors and/or one or more quantum processors. The system may autonomously select between types of hardware devices and/or types of heuristic optimization algorithms. Such may coordinate or at least partially overlap post-processing operations with processing operations, for instance performing post-processing on an ith batch of samples while generating an (i+1)th batch of samples, e.g., so post-processing operation on the ith batch of samples does not extend in time beyond the generation of the (i+1)th batch of samples. Heuristic optimizers selection is based on pre-processing assessment of the problem, e.g., based on features extracted from the problem and for instance, on predicted success.
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2.发明申请公开(公告)号：US20170178017A1
公开(公告)日：2017-06-22
申请号：US15338915
申请日：2016-10-31
Applicant: D-Wave Systems Inc.
Inventor： Aidan Patrick Roy , William G. Macready
Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.
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公开(公告)号：US10268622B2
公开(公告)日：2019-04-23
申请号：US15418497
申请日：2017-01-27
Applicant: D-Wave Systems Inc.
Inventor： Jeremy P. Hilton , Aidan Patrick Roy , Paul I. Bunyk , Andrew Douglas King , Kelly T. R. Boothby , Richard G. Harris , Chunqing Deng
Abstract: Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.
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4.发明授权Systems and methods that formulate embeddings of problems for solving by a quantum processor 有权制定和量化处理器解决问题嵌入的系统和方法公开(公告)号：US09501747B2
公开(公告)日：2016-11-22
申请号：US14109663
申请日：2013-12-17
Applicant: D-Wave Systems Inc.
Inventor： Aidan Patrick Roy
CPC classification number: G06N99/002 , B82Y10/00 , G06N5/003 , G06N99/005
Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.
Abstract translation: 系统和方法允许通过目标硬件（例如特定的量子处理器）来制定问题的嵌入。 在第一阶段中，连续生成一组连接的子图，每个集合包括问题图中每个决策变量的相应子图，映射到硬件图中相应顶点的问题图中的相邻决策变量，连接的相应顶点 通过硬件图中的至少一个相应边缘。 在第二阶段，连接的子图被细化，使得没有顶点表示多于单个决策变量。
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Patent Agency Ranking
5.发明申请公开(公告)号：US20140324933A1
公开(公告)日：2014-10-30
申请号：US14109657
申请日：2013-12-17
Applicant: D-Wave Systems Inc.
Inventor： William Macready , Aidan Patrick Roy
IPC: G06F17/10
CPC classification number: G06F17/10 , G06N99/002
Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.
Abstract translation: 系统和方法通过使用硬件图分解的量子处理器来解决问题。 原始图形的分解可以基于硬件特定图形建立在第一阶段中，并且在第二阶段通过例如从分解中去除顶点来进行细化。 硬件特定图可以是特定于一块硬件的图，例如包括多个量子位和可耦合器的量子处理器，其可操作地通信地耦合成对的量子位。
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6.发明申请SYSTEMS AND METHODS THAT FORMULATE EMBEDDINGS OF PROBLEMS FOR SOLVING BY A QUANTUM PROCESSOR 有权用于量子处理器解决问题的嵌入问题的系统和方法公开(公告)号：US20140250288A1
公开(公告)日：2014-09-04
申请号：US14109663
申请日：2013-12-17
Applicant: D-Wave Systems Inc.
Inventor： Aidan Patrick Roy
IPC: G06F9/30
CPC classification number: G06N99/002 , B82Y10/00 , G06N5/003 , G06N99/005
Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.
Abstract translation: 系统和方法允许通过目标硬件（例如特定的量子处理器）来制定问题的嵌入。 在第一阶段中，连续生成一组连接的子图，每个集合包括问题图中每个决策变量的相应子图，映射到硬件图中相应顶点的问题图中的相邻决策变量，连接的相应顶点 通过硬件图中的至少一个相应边缘。 在第二阶段，连接的子图被细化，使得没有顶点表示多于单个决策变量。
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公开(公告)号：US09875215B2
公开(公告)日：2018-01-23
申请号：US14109657
申请日：2013-12-17
Applicant: D-Wave Systems Inc.
Inventor： William Macready , Aidan Patrick Roy
CPC classification number: G06F17/10 , G06N99/002
Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.
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公开(公告)号：US20170255872A1
公开(公告)日：2017-09-07
申请号：US15505522
申请日：2015-08-21
Applicant: D-Wave Systems Inc.
Inventor： Firas Hamze , Andrew Douglas King , Jack Raymond , Aidan Patrick Roy , Robert Israel , Evgeny Andriyash , Catherine McGeoch , Mani Ranjbar
CPC classification number: G06N99/002 , G06F9/02 , G06F9/32 , G06F15/18 , G06F15/76 , G06F17/10 , G06N3/12
Abstract: Computational systems implement problem solving using heuristic solvers or optimizers. Such may iteratively evaluate a result of processing, and modify the problem or representation thereof before repeating processing on the modified problem, until a termination condition is reached. Heuristic solvers or optimizers may execute on one or more digital processors and/or one or more quantum processors. The system may autonomously select between types of hardware devices and/or types of heuristic optimization algorithms. Such may coordinate or at least partially overlap post-processing operations with processing operations, for instance performing post-processing on an ith batch of samples while generating an (i+1)th batch of samples, e.g., so post-processing operation on the ith batch of samples does not extend in time beyond the generation of the (i+1)th batch of samples. Heuristic optimizers selection is based on pre-processing assessment of the problem, e.g., based on features extracted from the problem and for instance, on predicted success.
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公开(公告)号：US20170220510A1
公开(公告)日：2017-08-03
申请号：US15418497
申请日：2017-01-27
Applicant: D-Wave Systems Inc.
Inventor： Jeremy P. Hilton , Aidan Patrick Roy , Paul I. Bunyk , Andrew Douglas King , Tomas J. Boothby , Richard G. Harris , Chunqing Deng
CPC classification number: G06F13/4068 , G06F13/36 , G06N99/002
Abstract: Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.
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