公开(公告)号：US20160351708A1

公开(公告)日：2016-12-01

申请号：US15039564

申请日：2014-12-17

Applicant: DENSO CORPORATION

Inventor： Hiroshi KAMEOKA ,  Shigeki TAKAHASHI ,  Akira YAMADA ,  Atsushi KASAHARA

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/7824 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66681

Abstract: A semiconductor device includes a lateral transistor having: a semiconductor substrate including a drift layer; a first impurity layer in the drift layer; a channel layer in the drift layer; a second impurity layer in the channel layer; a separation insulation film on the drift layer between the channel layer and the first impurity layer; a gate insulation film on a channel region between the second impurity layer and the drift layer connected with the separation insulation film; a gate electrode on the gate insulation film and the separation insulation film; a first electrode connected with the first impurity layer; a second electrode connected with the second impurity layer and the channel layer; and a field plate on the separation insulation film between the gate electrode and the first electrode and connected with the first electrode. The field plate is larger than the gate electrode in a current direction.

Abstract translation: 一种半导体器件包括横向晶体管，其具有：包括漂移层的半导体衬底; 漂移层中的第一杂质层; 漂移层中的沟道层; 沟道层中的第二杂质层; 在沟道层和第一杂质层之间的漂移层上的分离绝缘膜; 在第二杂质层与与分离绝缘膜连接的漂移层之间的沟道区上的栅极绝缘膜; 栅绝缘膜上的栅电极和分离绝缘膜; 与第一杂质层连接的第一电极; 与第二杂质层和沟道层连接的第二电极; 以及在栅电极和第一电极之间的分离绝缘膜上的与第一电极连接的场板。 场板在电流方向上大于栅电极。

公开(公告)号：US20190229219A1

公开(公告)日：2019-07-25

申请号：US16368026

申请日：2019-03-28

Applicant: DENSO CORPORATION

Inventor： Shinichirou YANAGI ,  Yusuke NONAKA ,  Seiji NOMA ,  Shinya SAKURAI ,  Shogo IKEURA ,  Atsushi KASAHARA ,  Shin TAKIZAWA

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/868 ,  H01L21/223 ,  H01L21/265

Abstract: A semiconductor device includes: a semiconductor substrate having a diode formation region; an upper diffusion region of a first conductivity type provided on a surface layer of a main surface of the semiconductor substrate in the diode formation region; and a lower diffusion region of a second conductivity type provided at a position deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, the lower diffusion region having a higher impurity concentration as compared to the semiconductor substrate. The lower diffusion region provides a PN joint surface with the upper diffusion region at a position deeper than the main surface, and has a maximum point indicating a maximum concentration in an impurity concentration profile of the lower diffusion region in the diode formation region.

公开(公告)号：US20210074631A1

公开(公告)日：2021-03-11

申请号：US17084854

申请日：2020-10-30

Applicant: DENSO CORPORATION

Inventor： Shin TAKIZAWA ,  Seiji NOMA ,  Yusuke NONAKA ,  Shinichirou YANAGI ,  Atsushi KASAHARA ,  Shogo IKEURA

IPC: H01L23/522

Abstract: On a substrate, a wiring layer is arranged by sequentially stacking a first insulation film, a lower electrode, a second insulation film, an intermediate electrode, a third insulation film, and an upper electrode in this order. A capacitor includes a first capacitor having the lower electrode and the intermediate electrode, and a second capacitor having the intermediate electrode and the upper electrode. The first capacitor and the second capacitor are connected in parallel to each other by electrically connecting the lower electrode and the upper electrode. Further, the intermediate electrode has a higher potential than the lower layer electrode and the upper electrode.

公开(公告)号：US20210028277A1

公开(公告)日：2021-01-28

申请号：US17066743

申请日：2020-10-09

Applicant: DENSO CORPORATION

Inventor： Shin TAKIZAWA ,  Yusuke NONAKA ,  Shinichirou YANAGI ,  Atsushi KASAHARA ,  Shogo IKEURA

IPC: H01L29/06 ,  H01L29/866 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface.