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公开(公告)号：US06591369B1
公开(公告)日：2003-07-08
申请号：US09410638
申请日：1999-10-01
IPC分类号： G06F1342
CPC分类号： G06F11/3636 , G01R31/31903 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
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公开(公告)号：US06530047B1
公开(公告)日：2003-03-04
申请号：US09411815
申请日：1999-10-01
IPC分类号： G01R3128
CPC分类号： G01R31/31903
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
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3.发明授权Microcomputer having address diversion means for remapping an on-chip device to an external port 有权具有用于将片上设备重映射到外部端口的地址转移装置的微型计算机公开(公告)号：US06457124B1
公开(公告)日：2002-09-24
申请号：US09268073
申请日：1999-03-12
IPC分类号： G06F900
CPC分类号： G06F11/3648
摘要： A single integrated circuit chip connected to an external computer device. The chip includes a CPU with registers, a bus for addressing devices assigned to a memory address space of the CPU and providing a parallel path between the CPU and a first memory local to the CPU, an address memory for storing addresses assigned to the devices, and an external port connected to the bus. The port includes an internal parallel signal format connection to the bus and a less parallel external connection to the external computer device. The port forms part of the memory address space of the CPU. The external computer device includes a second memory local to the external computer device and accessible by the CPU through the port. Address diversion means are provided for reconfiguring the memory address space of the CPU to assign to the port memory addresses of another one of the devices.
摘要翻译： 连接到外部计算机设备的单个集成电路芯片。 芯片包括具有寄存器的CPU，用于寻址分配给CPU的存储器地址空间的设备的总线，并且在CPU和CPU之间的第一存储器之间提供并行路径，用于存储分配给设备的地址的地址存储器， 和连接到总线的外部端口。 该端口包括与总线的内部并行信号格式连接，并且与外部计算机设备的并行外部连接较少。 端口构成CPU的内存地址空间的一部分。 外部计算机设备包括本地到外部计算机设备的第二存储器，并且可以由CPU通过端口访问。 提供地址转移装置用于重新配置CPU的存储器地址空间以分配给另一个设备的端口存储器地址。
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公开(公告)号：US08479039B2
公开(公告)日：2013-07-02
申请号：US13187061
申请日：2011-07-20
申请人： David Alan Edwards , Joe Woodward
发明人： David Alan Edwards , Joe Woodward
IPC分类号： G06F11/00
CPC分类号： G06F9/4403 , G06F11/1068 , G06F11/1417
摘要： The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
摘要翻译： 本发明提供一种防止引导存储器中的错误的方法，所述方法包括：通过从主引导存储器执行主引导代码并基于主引导代码的执行来启动处理器的引导：访问包括 存储在次启动存储器上的引导信息的多个冗余部分; 对多个部分执行错误检查以确定这些部分是否包含错误，并且基于错误检查来识别有效部分; 并使用引导信息的有效部分引导处理器。
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公开(公告)号：US08321718B2
公开(公告)日：2012-11-27
申请号：US12275375
申请日：2008-11-21
申请人： David Alan Edwards
发明人： David Alan Edwards
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/329 , G06F9/3851 , G06F9/3869 , G06F9/4843 , G06F9/4893 , Y02D10/126 , Y02D10/24
摘要： The present invention provides a processor comprising: an execution unit arranged to execute a plurality of program threads, clock generating means for generating first and second clock signals, and storage means for storing at least one thread-specific clock-control bit. The execution unit is configured to execute a first one of the threads in dependence on the first clock signal and to execute a second one of the threads in dependence on the second clock signal. The clock generating means is operable to generate the second clock signal with the second frequency selectively differing from the first frequency in dependence on the at least one clock-control bit. A corresponding method and computer program product are also provided.
摘要翻译： 本发明提供了一种处理器，包括：执行单元，被配置为执行多个程序线程，用于产生第一和第二时钟信号的时钟产生装置，以及用于存储至少一个线程专用时钟控制位的存储装置。 执行单元被配置为根据第一时钟信号执行线程中的第一个，并根据第二时钟信号执行线程中的第二个。 时钟产生装置可操作以产生第二时钟信号，其中第二频率选择性地与第一频率不同，这取决于至少一个时钟控制位。 还提供了相应的方法和计算机程序产品。
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公开(公告)号：US07996711B2
公开(公告)日：2011-08-09
申请号：US12323563
申请日：2008-11-26
申请人： David Alan Edwards , Joe Woodward
发明人： David Alan Edwards , Joe Woodward
IPC分类号： G06F11/00
CPC分类号： G06F9/4403 , G06F11/1068 , G06F11/1417
摘要： The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
摘要翻译： 本发明提供一种防止引导存储器中的错误的方法，所述方法包括：通过从主引导存储器执行主引导代码并基于主引导代码的执行来启动处理器的引导：访问包括 存储在次启动存储器上的引导信息的多个冗余部分; 对多个部分执行错误检查以确定这些部分是否包含错误，并且基于错误检查来识别有效部分; 并使用引导信息的有效部分引导处理器。
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公开(公告)号：US06601189B1
公开(公告)日：2003-07-29
申请号：US09410732
申请日：1999-10-01
IPC分类号： G06F1100
CPC分类号： G01R31/31903 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
摘要翻译： 提供了一种与集成电路通信的系统和方法，其允许集成电路与外部系统通信调试信息和系统总线事务信息。 该系统可以包括在集成电路和外部系统之间提供流量控制的接口协议。 系统可以包括用于传送信息的高速链路和/或JTAG链路。 链路可以由调试电路自动选择，或由片上设备或外部系统选择。 高速链路可实时追踪跟踪信息。 链路可以是存储器映射的，使得连接到系统总线的片上设备和其他设备可以访问外部系统。 高速链路也可以以与处理器或系统总线的速率整体耦合的速率工作。 此外，高速链路可以适应于响应于系统总线或处理器的操作速度的变化来改变速度。 JTAG接口可以使用标准的JTAG组件和指令，使得诸如使用这些组件和指令的调试适配器的外部设备可以被重新用于不同的集成电路类型。 通过JTAG或高速链路发送的信息可以被压缩以优化链路的可用带宽。 此外，处理器控制信号可以通过允许外部系统操纵和监视处理器及其相关模块的操作的链路传送。
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8.发明授权Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port 有权具有片上CPU的微处理器响应于通过调试端口接收到的控制信号从外部调试设备中的存储器获取调试例程公开(公告)号：US06356960B1
公开(公告)日：2002-03-12
申请号：US09710775
申请日：2000-11-09
IPC分类号： G06F1314
CPC分类号： G06F11/3656
摘要： There is disclosed a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a debugging port connected to a communication bus on the integrated circuit and to an external debugging computer device. The external debugging device is operable to transmit control signals through the debugging port: a) to stop execution by the CPU of instructions obtained from a first on-chip memory; b) to provide from a second memory associated with the external debugging computer device a debugging routine to be executed by the CPU; and c) to restart operation of the CPU after the routine with execution of instructions from an address determined by the external debugging device. The on-chip CPU is operable with code in the first memory which is independent of the debugging routine. A method of operating such a computer system with an external debugging device is also disclosed.
摘要翻译： 公开了一种包括在集成电路芯片上的微处理器的计算机系统，该集成电路芯片包括片上CPU和连接到集成电路上的通信总线的调试端口以及外部调试计算机设备。 外部调试装置可操作以通过调试端口发送控制信号：a）停止CPU执行从第一片上存储器获得的指令; b）从与外部调试计算机设备相关联的第二存储器提供要由CPU执行的调试例程; 以及c）在从由外部调试装置确定的地址执行指令的例程之后重新启动CPU的操作。 片上CPU可操作于独立于调试例程的第一存储器中的代码。 还公开了一种使用外部调试装置操作这种计算机系统的方法。
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公开(公告)号：US20090138754A1
公开(公告)日：2009-05-28
申请号：US12323563
申请日：2008-11-26
申请人： David Alan Edwards , Joe Woodward
发明人： David Alan Edwards , Joe Woodward
CPC分类号： G06F9/4403 , G06F11/1068 , G06F11/1417
摘要： The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
摘要翻译： 本发明提供一种防止引导存储器中的错误的方法，所述方法包括：通过从主引导存储器执行主引导代码并基于主引导代码的执行来启动处理器的引导：访问包括 存储在次启动存储器上的引导信息的多个冗余部分; 对多个部分执行错误检查以确定这些部分是否包含错误，并且基于错误检查来识别有效部分; 并使用引导信息的有效部分引导处理器。
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公开(公告)号：US06918065B1
公开(公告)日：2005-07-12
申请号：US09411794
申请日：1999-10-01
CPC分类号： G06F11/348
摘要： A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
摘要翻译： 提供用于执行非侵入性跟踪的系统，其从一个或多个处理器接收跟踪信息。 跟踪系统可以由用户配置为以各种模式操作以灵活地存储或发送跟踪信息。 跟踪系统包括一个内存映射的FIFO，可以在不影响处理器性能的情况下被访问。 在一个方面，跟踪系统包括跟踪缓冲器，其以处理器的内部时钟速度接收跟踪信息。 在另一个实施例中，提供了压缩协议，用于在将消息发送到外部系统之前或在存储器中存储消息的情况下在片上缓存跟踪消息。
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