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公开(公告)号：US06530047B1
公开(公告)日：2003-03-04
申请号：US09411815
申请日：1999-10-01
IPC分类号： G01R3128
CPC分类号： G01R31/31903
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
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公开(公告)号：US06859891B2
公开(公告)日：2005-02-22
申请号：US09410606
申请日：1999-10-01
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.
摘要翻译： 提供一种包括处理器和调试电路的微计算机，该调试电路包括专用链路，该专用链路在处理器和调试电路之间传送信息以支持调试操作 在一个方面，处理器提供存储在调试电路的存储器映射寄存器中的程序计数器信息。 程序计数器信息可以是处理器管线的回写阶段处理器程序计数器的值。 此外，包括消息信息的跟踪信息通过专用链路以非侵入方式传送。 一方面，微型计算机被实现为单个集成电路。
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公开(公告)号：US06779145B1
公开(公告)日：2004-08-17
申请号：US09410860
申请日：1999-10-01
IPC分类号： G01R3128
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG-or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
摘要翻译： 提供了一种用于与集成电路通信的系统和方法，其允许集成电路与外部系统通信调试信息和系统总线事务信息。 该系统可以包括在集成电路和外部系统之间提供流量控制的接口协议。 该系统可以包括用于传送信息的高速链路和/或JTAG链路。 链路可以由调试电路自动选择，或由片上设备或外部系统选择。 高速链路可实时追踪跟踪信息。 链路可以是存储器映射的，使得连接到系统总线的片上设备和其他设备可以访问外部系统。 高速链路也可以以与处理器或系统总线的速率整体耦合的速率工作。 此外，高速链路可以适应于响应于系统总线或处理器的操作速度的变化来改变速度。 JTAG接口可以使用标准的JTAG组件和指令，使得诸如使用这些组件和指令的调试适配器的外部设备可以被重新用于不同的集成电路类型。 通过JTAG或高速链路发送的信息可以被压缩以优化链路的可用带宽。 此外，处理器控制信号可以通过允许外部系统操纵和监视处理器及其相关模块的操作的链路传送。
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公开(公告)号：US06601189B1
公开(公告)日：2003-07-29
申请号：US09410732
申请日：1999-10-01
IPC分类号： G06F1100
CPC分类号： G01R31/31903 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
摘要翻译： 提供了一种与集成电路通信的系统和方法，其允许集成电路与外部系统通信调试信息和系统总线事务信息。 该系统可以包括在集成电路和外部系统之间提供流量控制的接口协议。 系统可以包括用于传送信息的高速链路和/或JTAG链路。 链路可以由调试电路自动选择，或由片上设备或外部系统选择。 高速链路可实时追踪跟踪信息。 链路可以是存储器映射的，使得连接到系统总线的片上设备和其他设备可以访问外部系统。 高速链路也可以以与处理器或系统总线的速率整体耦合的速率工作。 此外，高速链路可以适应于响应于系统总线或处理器的操作速度的变化来改变速度。 JTAG接口可以使用标准的JTAG组件和指令，使得诸如使用这些组件和指令的调试适配器的外部设备可以被重新用于不同的集成电路类型。 通过JTAG或高速链路发送的信息可以被压缩以优化链路的可用带宽。 此外，处理器控制信号可以通过允许外部系统操纵和监视处理器及其相关模块的操作的链路传送。
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公开(公告)号：US20120137145A1
公开(公告)日：2012-05-31
申请号：US13387066
申请日：2010-07-23
CPC分类号： H04L12/403 , G06F11/1441
摘要： A system comprises a central processing unit (10), an interconnection bus (1), and a plurality of functional modules (11-15, 21) corresponding to distinct power domains and able to communicate with each other and/or with the central processing unit via the bus. At least one of the power domains, and is configured to be substituted for a slave functional module (21) of the power domain when the power to the power domain is turned off by the central processing unit. It signals an error in response to any request of a transaction that is in progress between the slave functional module and a master functional module at the moment the power is turned off.
摘要翻译： 一种系统包括中央处理单元（10），互连总线（1）和对应于不同功率域并且能够彼此通信和/或中央处理的多个功能模块（11-15,21） 通过公共汽车单位。 至少一个功率域，并且被配置为由功率域的从功能模块（21）代替功率域的功率由中央处理单元关闭。 它响应于在电源关闭时在从功能模块和主功能模块之间正在进行的事务的任何请求的响应中发出错误。
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公开(公告)号：US08832471B2
公开(公告)日：2014-09-09
申请号：US13387066
申请日：2010-07-23
IPC分类号： G06F1/00 , G06F1/32 , H03K17/16 , H04L12/403 , G06F11/14
CPC分类号： H04L12/403 , G06F11/1441
摘要： A system comprises a central processing unit (10), an interconnection bus (1), and a plurality of functional modules (11-15, 21) corresponding to distinct power domains and able to communicate with each other and/or with the central processing unit via the bus. At least one of the power domains, and is configured to be substituted for a slave functional module (21) of the power domain when the power to the power domain is turned off by the central processing unit. It signals an error in response to any request of a transaction that is in progress between the slave functional module and a master functional module at the moment the power is turned off.
摘要翻译： 一种系统包括中央处理单元（10），互连总线（1）和对应于不同功率域并且能够彼此通信和/或中央处理的多个功能模块（11-15,21） 通过公共汽车单位。 至少一个功率域，并且被配置为由功率域的从功能模块（21）代替功率域的功率由中央处理单元关闭。 它响应于在电源关闭时在从功能模块和主功能模块之间正在进行的事务的任何请求的响应中发出错误。
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公开(公告)号：US06701405B1
公开(公告)日：2004-03-02
申请号：US09410927
申请日：1999-10-01
申请人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
发明人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
IPC分类号： G06F1336
CPC分类号： G06F13/28
摘要： A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC. In response to the request signal, the DMAC implements a DMA transfer according to the values stored in the DMAC configuration registers. Peripheral-specific signaling is provided to the system component by the peripheral request interface
摘要翻译： 具有用于实现DMA传输的简单握手协议的计算机系统。 提供一种系统总线，其具有用于耦合到包括存储器，中央处理单元和外围设备的系统组件的多个端口。 直接存储器访问控制器（DMAC）具有耦合到系统总线的与外设无关的接口，并使用系统总线定义的事务与系统总线进行通信。 DMAC包括一组寄存器。 中央处理单元（CPU）通过将值加载到DMAC寄存器中来配置DMAC。 配置的DMAC向DMAC寄存器中标识的所选系统组件发出使能信号。 外围设备请求接口与所选系统组件相关联，并使用系统总线定义的事务与系统总线进行通信。 所选系统组件向DMAC发出请求信号。 响应于请求信号，DMAC根据存储在DMAC配置寄存器中的值实现DMA传输。 通过外设请求接口向系统组件提供外设特定的信令
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公开(公告)号：US06349371B1
公开(公告)日：2002-02-19
申请号：US09411800
申请日：1999-10-01
IPC分类号： G06F1200
CPC分类号： G06F11/364 , G06F11/3485
摘要： In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.
摘要翻译： 在包括连接到互连的互连和多个模块的系统中，用于控制所述模块中的哪一个能够将信息放置在所述互连上的电路，所述电路包括存储每个模块的状态信息的存储器，所述状态信息定义 如果允许相应的模块将信息放在所述互连上。
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公开(公告)号：US6091664A
公开(公告)日：2000-07-18
申请号：US325139
申请日：1999-06-03
申请人： Bernard Ramanadin
发明人： Bernard Ramanadin
CPC分类号： H03K3/037
摘要： A substitution circuit for elementary flip-flop circuits is provided to enable the automatic transposition of a flip-flop circuit whose clock signal comes from a combinational logic circuit. To do this, an over-sampled internal clock signal is used along with a synchronous pulse generator to validate the data.
摘要翻译： 提供了用于基本触发器电路的替代电路，以便能够自动转置其时钟信号来自组合逻辑电路的触发器电路。 为了做到这一点，过采样的内部时钟信号与同步脉冲发生器一起使用以验证数据。
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10.发明授权Output buffer register, electronic circuit and method for delivering signals using same 有权输出缓冲寄存器，电子电路和使用其传送信号的方法公开(公告)号：US07016988B2
公开(公告)日：2006-03-21
申请号：US10701115
申请日：2003-11-04
申请人： Bernard Ramanadin
发明人： Bernard Ramanadin
CPC分类号： G11C7/1054 , G06F5/00 , G06F13/4072 , G11C7/1051 , G11C7/106
摘要： An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.
摘要翻译： 输出缓冲寄存器包括接收给定数量N个输入信号的第一输入触发器寄存器，锁存寄存器，选择寄存器和输出N个输出信号的输出多路复用器。 使能寄存器只有一个数据输入端接收使能信号。 以这种方式，缓冲寄存器的输入端的传播时间减少。
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