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1.发明授权Electronic learning synapse with spike-timing dependent plasticity using memory-switching elements 有权使用存储器开关元件的具有尖峰时序依赖性塑性的电子学习突触公开(公告)号：US08682822B2
公开(公告)日：2014-03-25
申请号：US13527043
申请日：2012-06-19
CPC分类号： G06N3/049 , G06N3/0635
摘要： A system, method and computer program product produce spike-dependent plasticity in an artificial synapse. A method includes: an electronic device generating a pre-synaptic pulse that occurs a predetermined period of time after receiving a pre-synaptic spike at a first input. The electronic device generating a post-synaptic pulse that starts at a baseline value and reaches a first voltage value a first period of time after receiving a post-synaptic spike at a second input, followed by a second voltage value a second period of time after the post synaptic spike, followed by a return to said baseline voltage a third period of time after the post-synaptic spike. The generated pre-synaptic pulse is applied to a pre-synaptic node of a synaptic device in series with a rectifying element that has a turn-on voltage based on a threshold. The generated post-synaptic pulse is applied to a post-synaptic node of said synaptic device.
摘要翻译： 系统，方法和计算机程序产品在人造突触中产生尖峰依赖的可塑性。 一种方法包括：电子装置，其在接收到在第一输入端的突触前尖峰之前产生预定时间段的预触发脉冲。 所述电子设备产生突触后脉冲，其在基线值开始并在第二输入接收到突触后尖峰之后的第一时间段达到第一电压值，之后是在第二时间段之后的第二电压值 后突触尖峰，之后是在突触后尖峰之后的第三个时间段内返回到所述基线电压。 产生的突触前脉冲被施加到突触装置的突触前节点，其与具有基于阈值的导通电压的整流元件串联。 产生的突触后脉冲被施加到所述突触装置的突触后节点。
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2.发明申请ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING MEMORY-SWITCHING ELEMENTS 有权使用存储器切换元件的SPIKE-TIMING相关塑料的电子学习实验公开(公告)号：US20120265719A1
公开(公告)日：2012-10-18
申请号：US13527043
申请日：2012-06-19
CPC分类号： G06N3/049 , G06N3/0635
摘要： A system, method and computer program product produce spike-dependent plasticity in an artificial synapse. A method includes: an electronic device generating a pre-synaptic pulse that occurs a predetermined period of time after receiving a pre-synaptic spike at a first input. The electronic device generating a post-synaptic pulse that starts at a baseline value and reaches a first voltage value a first period of time after receiving a post-synaptic spike at a second input, followed by a second voltage value a second period of time after the post synaptic spike, followed by a return to said baseline voltage a third period of time after the post-synaptic spike. The generated pre-synaptic pulse is applied to a pre-synaptic node of a synaptic device in series with a rectifying element that has a turn-on voltage based on a threshold. The generated post-synaptic pulse is applied to a post-synaptic node of said synaptic device.
摘要翻译： 系统，方法和计算机程序产品在人造突触中产生尖峰依赖的可塑性。 一种方法包括：电子装置，其在接收到在第一输入端的突触前尖峰之前产生预定时间段的预触发脉冲。 所述电子设备产生突触后脉冲，其在基线值开始并在第二输入接收到突触后尖峰之后的第一时间段达到第一电压值，之后是在第二时间段之后的第二电压值 后突触尖峰，之后是在突触后尖峰之后的第三个时间段内返回到所述基线电压。 产生的突触前脉冲被施加到突触装置的突触前节点，其与具有基于阈值的导通电压的整流元件串联。 产生的突触后脉冲被施加到所述突触装置的突触后节点。
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3.发明申请ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING UNIPOLAR MEMORY-SWITCHING ELEMENTS 有权使用单核存储器切换元件的具有SPIKE时序依赖性塑性的电子学习算法公开(公告)号：US20100299296A1
公开(公告)日：2010-11-25
申请号：US12470403
申请日：2009-05-21
CPC分类号： G06N3/049 , G06N3/0635
摘要： According to embodiments of the invention, a system, method and computer program product producing spike-dependent plasticity in an artificial synapse. In an embodiment, a method includes: receiving a pre-synaptic spike in an electronic component; receiving a post-synaptic spike in the electronic component; in response to the pre-synaptic spike, generating a pre-synaptic pulse that occurs a predetermined period of time after the received pre-synaptic spike; in response to the post-synaptic spike, generating a post-synaptic pulse that starts at a baseline value and reaches a first voltage value a first period of time after the post-synaptic spike, followed by a second voltage value a second period of time after the post synaptic spike, followed by a return to the baseline voltage a third period of time after the post-synaptic spike; applying the generated pre-synaptic pulse to a pre-synaptic node of a synaptic device that includes a uni-polar, two-terminal bi-stable device in series with a rectifying element; and applying the generated post-synaptic pulse to a post-synaptic node of the synaptic device, wherein the synaptic device changes from a first conductive state to a second conductive state based on the value of input voltage applied to its pre and post-synaptic nodes, wherein the resultant state of the conductance of the synaptic device after the pre- and post-synaptic pulses are applied thereto depends on the relative timing of the received pre-synaptic spike with respect to the post synaptic spike.
摘要翻译： 根据本发明的实施例，在人造突触中产生尖峰依赖可塑性的系统，方法和计算机程序产品。 在一个实施例中，一种方法包括：在电子部件中接收突触前突起; 接收电子元件中的突触后尖峰; 响应于突触前尖峰，产生在接收到的突触前尖峰之后发生预定时间段的突触前脉冲; 响应于突触后尖峰，产生在基线值开始并在突触后尖峰之后的第一时间段达到第一电压值的后突触后脉冲，随后是第二时间段的第二电压值 后突触尖峰后，再次回到基线电压第三个时间段后突触后尖峰; 将产生的突触前脉冲应用于包括与整流元件串联的单极性双端双稳态器件的突触器件的突触前节点; 以及将所产生的突触后脉冲应用于所述突触装置的突触后结点，其中所述突触装置基于施加到其前和后突触节点的输入电压的值从第一导通状态改变到第二导通状态 其中将突触前装置和突触后脉冲之后的突触装置的电导的结果状态施加到其上取决于所接收的突触前尖峰相对于突触后尖峰的相对时间。
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公开(公告)号：US20080314738A1
公开(公告)日：2008-12-25
申请号：US11765142
申请日：2007-06-19
CPC分类号： H01L45/142 , C23C18/1204 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1608
摘要： The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.
摘要翻译： 本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。 无定形硫族化物固体活性电解质层位于第一和第二金属层之间。 无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的， 将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。 本公开还涉及制造固体电解质器件的方法。
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公开(公告)号：US07928419B2
公开(公告)日：2011-04-19
申请号：US11830213
申请日：2007-07-30
CPC分类号： H01L45/142 , C23C18/1204 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1608
摘要： The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.
摘要翻译： 本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。 无定形硫族化物固体活性电解质层位于第一和第二金属层之间。 无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的， 将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。 本公开还涉及制造固体电解质器件的方法。
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公开(公告)号：US20130322153A1
公开(公告)日：2013-12-05
申请号：US13485748
申请日：2012-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译： 一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到 所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。 还介绍了其他系统和方法。
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7.发明申请BACKEND OF LINE (BEOL) COMPATIBLE HIGH CURRENT DENSITY ACCESS DEVICE FOR HIGH DENSITY ARRAYS OF ELECTRONIC COMPONENTS 有权线（BEOL）的兼容高电流密度访问设备用于电子元件的高密度阵列公开(公告)号：US20110227023A1
公开(公告)日：2011-09-22
申请号：US12727746
申请日：2010-03-19
IPC分类号： H01L45/00
CPC分类号： H01L45/00 , H01L27/2409 , H01L45/06 , H01L45/1233
摘要： A device is disclosed having a M8XY6 layer sandwiched in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Also disclosed is a device comprising: an MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and wherein a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.
摘要翻译： 公开了一种器件，其具有夹在顶部的第一导电层和底部的第二导电层之间的M8XY6层，其中（i）M包括选自由Cu，Ag，Li和 Zn，（ii）X包括至少一种XIV族，和（iii）Y包括至少一个XVI族。 还公开了一种装置，包括：MaXbYc材料，在相对侧通过相应的导电材料层接触，其中：（i）M包括选自由Cu，Ag，Li和Zn组成的组中的至少一种元素，（ii） X包括至少一个第XIV族元素，和（iii）Y包括至少一个第ⅩⅥ族元素，并且其中a在48-60原子百分比的范围内，b在4-10原子百分比的范围内，c是 在30-45原子％的范围内，a + b + c为至少90原子％。
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公开(公告)号：US20080314739A1
公开(公告)日：2008-12-25
申请号：US11830213
申请日：2007-07-30
IPC分类号： C25B9/06
CPC分类号： H01L45/142 , C23C18/1204 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1608
摘要： The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.
摘要翻译： 本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。 无定形硫族化物固体活性电解质层位于第一和第二金属层之间。 无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的， 将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。 本公开还涉及制造固体电解质器件的方法。
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公开(公告)号：US08811060B2
公开(公告)日：2014-08-19
申请号：US13485748
申请日：2012-05-31
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译： 一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到 所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。 还介绍了其他系统和方法。
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10.发明申请LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS 有权具有高电压容量的低温BEO兼容二极管用于大型电子元件阵列公开(公告)号：US20130044532A1
公开(公告)日：2013-02-21
申请号：US13209569
申请日：2011-08-15
申请人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
发明人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
CPC分类号： H01L29/872 , G11C13/003 , G11C2029/5002 , G11C2029/5006 , G11C2213/72 , H01L27/1021 , H01L27/224 , H01L27/2427 , H01L45/141 , H01L45/1616
摘要： A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
摘要翻译： 夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。 这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。
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