-
公开(公告)号：US08811060B2
公开(公告)日：2014-08-19
申请号：US13485748
申请日：2012-05-31
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译： 一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到 所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。 还介绍了其他系统和方法。
-
公开(公告)号：US20130322153A1
公开(公告)日：2013-12-05
申请号：US13485748
申请日：2012-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译： 一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到 所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。 还介绍了其他系统和方法。
-
3.发明申请LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS 有权具有高电压容量的低温BEO兼容二极管用于大型电子元件阵列公开(公告)号：US20130044532A1
公开(公告)日：2013-02-21
申请号：US13209569
申请日：2011-08-15
申请人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
发明人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
CPC分类号： H01L29/872 , G11C13/003 , G11C2029/5002 , G11C2029/5006 , G11C2213/72 , H01L27/1021 , H01L27/224 , H01L27/2427 , H01L45/141 , H01L45/1616
摘要： A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
摘要翻译： 夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。 这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。
-
公开(公告)号：US20080314738A1
公开(公告)日：2008-12-25
申请号：US11765142
申请日：2007-06-19
CPC分类号： H01L45/142 , C23C18/1204 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1608
摘要： The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.
摘要翻译： 本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。 无定形硫族化物固体活性电解质层位于第一和第二金属层之间。 无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的， 将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。 本公开还涉及制造固体电解质器件的方法。
-
公开(公告)号：US09812638B2
公开(公告)日：2017-11-07
申请号：US12727746
申请日：2010-03-19
CPC分类号： H01L45/00 , H01L27/2409 , H01L45/06 , H01L45/1233
摘要： A device has a M8XY6 layer in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Another device has MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.
-
公开(公告)号：US07928419B2
公开(公告)日：2011-04-19
申请号：US11830213
申请日：2007-07-30
CPC分类号： H01L45/142 , C23C18/1204 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1608
摘要： The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.
摘要翻译： 本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。 无定形硫族化物固体活性电解质层位于第一和第二金属层之间。 无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的， 将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。 本公开还涉及制造固体电解质器件的方法。
-
7.发明授权Low temperature BEOL compatible diode having high voltage margins for use in large arrays of electronic components 有权低温BEOL兼容二极管具有高电压裕度，可用于大型电子元件阵列公开(公告)号：US08830725B2
公开(公告)日：2014-09-09
申请号：US13209569
申请日：2011-08-15
申请人： Donald S Bethune , Kailash Gopalakrishnan , Andrew J Kellock , Rohit S Shenoy , Kumar R Virwani
发明人： Donald S Bethune , Kailash Gopalakrishnan , Andrew J Kellock , Rohit S Shenoy , Kumar R Virwani
IPC分类号： G11C11/00
CPC分类号： H01L29/872 , G11C13/003 , G11C2029/5002 , G11C2029/5006 , G11C2213/72 , H01L27/1021 , H01L27/224 , H01L27/2427 , H01L45/141 , H01L45/1616
摘要： A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
摘要翻译： 夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。 这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。
-
8.发明申请BACKEND OF LINE (BEOL) COMPATIBLE HIGH CURRENT DENSITY ACCESS DEVICE FOR HIGH DENSITY ARRAYS OF ELECTRONIC COMPONENTS 有权线（BEOL）的兼容高电流密度访问设备用于电子元件的高密度阵列公开(公告)号：US20110227023A1
公开(公告)日：2011-09-22
申请号：US12727746
申请日：2010-03-19
IPC分类号： H01L45/00
CPC分类号： H01L45/00 , H01L27/2409 , H01L45/06 , H01L45/1233
摘要： A device is disclosed having a M8XY6 layer sandwiched in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Also disclosed is a device comprising: an MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and wherein a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.
摘要翻译： 公开了一种器件，其具有夹在顶部的第一导电层和底部的第二导电层之间的M8XY6层，其中（i）M包括选自由Cu，Ag，Li和 Zn，（ii）X包括至少一种XIV族，和（iii）Y包括至少一个XVI族。 还公开了一种装置，包括：MaXbYc材料，在相对侧通过相应的导电材料层接触，其中：（i）M包括选自由Cu，Ag，Li和Zn组成的组中的至少一种元素，（ii） X包括至少一个第XIV族元素，和（iii）Y包括至少一个第ⅩⅥ族元素，并且其中a在48-60原子百分比的范围内，b在4-10原子百分比的范围内，c是 在30-45原子％的范围内，a + b + c为至少90原子％。
-
公开(公告)号：US20080314739A1
公开(公告)日：2008-12-25
申请号：US11830213
申请日：2007-07-30
IPC分类号： C25B9/06
CPC分类号： H01L45/142 , C23C18/1204 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/1608
摘要： The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device.
摘要翻译： 本公开内容涉及包含非晶态硫族化物固体活性电解质层的固体电解质装置; 第一和第二金属层。 无定形硫族化物固体活性电解质层位于第一和第二金属层之间。 无定形硫族化物固体活性电解质层是通过将金属硫属元素化合物的肼类前体溶液获得的， 将溶液施加到基底上; 然后使前体退火以将前体转化为无定形金属硫族化物。 本公开还涉及制造固体电解质器件的方法。
-
10.发明授权公开(公告)号：US07920406B2
公开(公告)日：2011-04-05
申请号：US12180586
申请日：2008-07-28
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译： 一种用于形成存储器结构的方法，包括：形成布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元还包括能够被编程为多个电阻状态的电阻性存储器件 每个电阻存储器件在其第一端处耦合到位线之一; 在其第二端配置与每个所述电阻式存储器件串联的整流元件; 配置与每个单独存储器单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及形成公共连接，其被配置为沿着字线方向将两个或更多个组的相邻整流装置短路在一起。
-
-
-
-
-
-
-
-
-
搜索结果
53 条记录 (耗时 0.024 秒)