公开(公告)号：US20130044532A1

公开(公告)日：2013-02-21

申请号：US13209569

申请日：2011-08-15

申请人： Donald S. Bethune ,  Kailash Gopalakrishnan ,  Andrew J. Kellock ,  Rohit S. Shenoy ,  Kumar R. Virwani

发明人： Donald S. Bethune ,  Kailash Gopalakrishnan ,  Andrew J. Kellock ,  Rohit S. Shenoy ,  Kumar R. Virwani

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L29/872 ,  G11C13/003 ,  G11C2029/5002 ,  G11C2029/5006 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/2427 ,  H01L45/141 ,  H01L45/1616

摘要： A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.

摘要翻译： 夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。 这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。

公开(公告)号：US20110227023A1

公开(公告)日：2011-09-22

申请号：US12727746

申请日：2010-03-19

申请人： Donald S. Bethune ,  Kailash Gopalakrishnan ,  Andrew J. Kellock ,  Rohit S. Shenoy

发明人： Donald S. Bethune ,  Kailash Gopalakrishnan ,  Andrew J. Kellock ,  Rohit S. Shenoy

IPC分类号： H01L45/00

CPC分类号： H01L45/00 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233

摘要： A device is disclosed having a M8XY6 layer sandwiched in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Also disclosed is a device comprising: an MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the group consisting of Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and wherein a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.

摘要翻译： 公开了一种器件，其具有夹在顶部的第一导电层和底部的第二导电层之间的M8XY6层，其中（i）M包括选自由Cu，Ag，Li和 Zn，（ii）X包括至少一种XIV族，和（iii）Y包括至少一个XVI族。 还公开了一种装置，包括：MaXbYc材料，在相对侧通过相应的导电材料层接触，其中：（i）M包括选自由Cu，Ag，Li和Zn组成的组中的至少一种元素，（ii） X包括至少一个第XIV族元素，和（iii）Y包括至少一个第ⅩⅥ族元素，并且其中a在48-60原子百分比的范围内，b在4-10原子百分比的范围内，c是 在30-45原子％的范围内，a + b + c为至少90原子％。

公开(公告)号：US20090071836A1

公开(公告)日：2009-03-19

申请号：US11856335

申请日：2007-09-17

申请人： Qiang Huang ,  Andrew J. Kellock ,  Xiaoyan Shao ,  Venkatram Venkatasamy

发明人： Qiang Huang ,  Andrew J. Kellock ,  Xiaoyan Shao ,  Venkatram Venkatasamy

IPC分类号： C25D7/12 ,  C25D5/02

CPC分类号： C25D7/12 ,  C25D3/54 ,  C25D5/022 ,  C25D5/18 ,  C25D17/001 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of electrodepositing germanium compound materials on an exposed region of a substrate structure, which includes forming a plating solution by dissolving at least one germanium salt and at least one salt containing an element other than germanium in water; obtaining a substrate with a clean surface; immersing the substrate in the solution; and electroplating germanium compound materials on the substrate by applying an electrical potential between the substrate and an anode in the plating solution, in which the substrate is included in a semiconductor or phase change device.

摘要翻译： 一种将锗化合物材料电沉积在基材结构的暴露区域上的方法，其包括通过将至少一种锗盐和至少一种含锗以外的元素的盐溶解在水中形成电镀溶液; 获得具有干净表面的基材; 将基材浸入溶液中; 以及通过在所述基板和所述基板被包括在半导体或相变装置中的所述电镀液中的所述基板和阳极之间施加电位而在所述基板上电镀锗化合物材料。

公开(公告)号：US07193323B2

公开(公告)日：2007-03-20

申请号：US10714966

申请日：2003-11-18

申请人： Cyril Cabral, Jr. ,  Stefanie R. Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew J. Kellock ,  Judith M. Rubino ,  Roger Y. Tsai

发明人： Cyril Cabral, Jr. ,  Stefanie R. Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew J. Kellock ,  Judith M. Rubino ,  Roger Y. Tsai

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

摘要翻译： 一种复合材料，其包含含有铜的层和在铜层上的电沉积CoWP膜。 CoWP膜含有11原子％至25原子％的磷并具有5nm至200nm的厚度。 本发明还涉及一种制造互连结构的方法，包括：在介电材料内提供沟槽或通孔，以及在沟槽或通孔内容纳铜的导电金属; 并通过电沉积在铜层上形成CoWP膜。 CoWP膜含有10原子％至25原子％的磷，并且具有5nm至200nm的厚度。 本发明还涉及包括与金属层接触的电介质层的互连结构; 金属层上的电沉积CoWP膜，CoWP膜上的铜层。

公开(公告)号：US06747845B1

公开(公告)日：2004-06-08

申请号：US09689050

申请日：2000-10-11

申请人： John Edward Eric Baglin ,  Richard D. Bunch ,  Linden James Crawforth ,  Eric W. Flint ,  Andrew J. Kellock ,  Timothy Clark Reiley

发明人： John Edward Eric Baglin ,  Richard D. Bunch ,  Linden James Crawforth ,  Eric W. Flint ,  Andrew J. Kellock ,  Timothy Clark Reiley

IPC分类号： G11B560

CPC分类号： G11B5/6005 ,  G11B5/102

摘要： At least one modified strain region having a damage depth between 0.1 and 2 microns in a disk drive slider is created by implantation with ions, electrons or neutral atoms. The modified strain region induces a deformation of the disk drive slider. The nature and extent of this deformation is determined by the interaction between the slider and the modified strain region.

摘要翻译： 通过用离子，电子或中性原子注入，在盘驱动器滑块中具有0.1至2微米之间的损伤深度的至少一个修改的应变区产生。 改性应变区域引起磁盘驱动器滑块的变形。 该变形的性质和程度由滑块与改性应变区之间的相互作用决定。

公开(公告)号：US08404589B2

公开(公告)日：2013-03-26

申请号：US12754912

申请日：2010-04-06

申请人： Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

发明人： Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.

摘要翻译： 形成硅化物接触的方法包括在硅上沉积金属层，使得金属层与硅混合以在硅上形成混合区; 从所述混合区域去除所述金属层的未混合部分; 并且对所述混合区进行退火以在所述硅上形成硅化物接触。 一种半导体器件，包括位于所述半导体器件的硅层上方的硅化物触点，所述硅化物触点包含镍（Ni）和硅（Si），并且具有相当于约21埃或更小的厚度的Ni量。

公开(公告)号：US07918984B2

公开(公告)日：2011-04-05

申请号：US11856335

申请日：2007-09-17

申请人： Qiang Huang ,  Andrew J. Kellock ,  Xiaoyan Shao ,  Venkatram Venkatasamy

发明人： Qiang Huang ,  Andrew J. Kellock ,  Xiaoyan Shao ,  Venkatram Venkatasamy

IPC分类号： C25D5/02

CPC分类号： C25D7/12 ,  C25D3/54 ,  C25D5/022 ,  C25D5/18 ,  C25D17/001 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of electrodepositing germanium compound materials on an exposed region of a substrate structure, which includes forming a plating solution by dissolving at least one germanium salt and at least one salt containing an element other than germanium in water; obtaining a substrate with a clean surface; immersing the substrate in the solution; and electroplating germanium compound materials on the substrate by applying an electrical potential between the substrate and an anode in the plating solution, in which the substrate is included in a semiconductor or phase change device.

摘要翻译： 一种将锗化合物材料电沉积在基材结构的暴露区域上的方法，其包括通过将至少一种锗盐和至少一种含锗以外的元素的盐溶解在水中形成电镀溶液; 获得具有干净表面的基材; 将基材浸入溶液中; 以及通过在所述基板和所述基板被包括在半导体或相变装置中的所述电镀液中的所述基板和阳极之间施加电位而在所述基板上电镀锗化合物材料。

公开(公告)号：US20110241213A1

公开(公告)日：2011-10-06

申请号：US12754912

申请日：2010-04-06

申请人： Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

发明人： Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.

摘要翻译： 形成硅化物接触的方法包括在硅上沉积金属层，使得金属层与硅混合以在硅上形成混合区; 从所述混合区域去除所述金属层的未混合部分; 并且对所述混合区进行退火以在所述硅上形成硅化物接触。 一种半导体器件，包括位于所述半导体器件的硅层上方的硅化物触点，所述硅化物触点包括镍（Ni）和硅（Si），并且具有相当于约21埃或更小的厚度的Ni量。

公开(公告)号：US20100055442A1

公开(公告)日：2010-03-04

申请号：US12203338

申请日：2008-09-03

申请人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

发明人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

IPC分类号： C23C16/513 ,  B32B3/26

CPC分类号： C23C16/45536 ,  C23C16/36 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/3141 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76831 ,  Y10T428/24999

摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.

摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。

公开(公告)号：US20120301706A1

公开(公告)日：2012-11-29

申请号：US13568808

申请日：2012-08-07

申请人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

发明人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

IPC分类号： C23C16/50 ,  B32B3/26

CPC分类号： C23C16/45536 ,  C23C16/36 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/3141 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76831 ,  Y10T428/24999

摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.

摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。