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公开(公告)号:US20050226032A1
公开(公告)日:2005-10-13
申请号:US10812894
申请日:2004-03-31
申请人: Stephen Tang , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz
发明人: Stephen Tang , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz
IPC分类号: G11C11/00
CPC分类号: G11C11/412
摘要: A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
摘要翻译: 提供具有多个存储单元的SRAM器件。 每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体,以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。 功率控制单元可以控制每个PMOS晶体管的电源电压,并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。
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公开(公告)号:US20060262610A1
公开(公告)日:2006-11-23
申请号:US11134450
申请日:2005-05-23
申请人: Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
发明人: Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
IPC分类号: G11C5/14
摘要: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
摘要翻译: 提供了一种降低集成存储器件功耗的方法和装置。 存储单元组可以通过相应的“睡眠”晶体管单独地进入“睡眠”模式。
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公开(公告)号:US20060067109A1
公开(公告)日:2006-03-30
申请号:US10956195
申请日:2004-09-30
申请人: Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen Tang , Vivek De
发明人: Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen Tang , Vivek De
CPC分类号: G11C11/413
摘要: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
摘要翻译: 描述了一种方法,其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。 电压超过另一个电压,运算放大器将驱动节点没有晶体管的帮助。 电压有助于反馈回路在SRAM内的单元上建立一个压降。
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公开(公告)号:US20060104128A1
公开(公告)日:2006-05-18
申请号:US11320789
申请日:2005-12-30
申请人: Dinesh Somasekhar , Muhammad Khellah , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
发明人: Dinesh Somasekhar , Muhammad Khellah , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
IPC分类号: G11C7/10
CPC分类号: G11C5/143 , G11C5/147 , G11C11/413
摘要: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
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公开(公告)号:US20050135162A1
公开(公告)日:2005-06-23
申请号:US10738216
申请日:2003-12-18
申请人: Dinesh Somasekhar , Muhammad Khellah , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
发明人: Dinesh Somasekhar , Muhammad Khellah , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
IPC分类号: G11C5/00 , G11C5/14 , G11C11/413
CPC分类号: G11C5/143 , G11C5/147 , G11C11/413
摘要: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
摘要翻译: 提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。 该装置可以包括存储器阵列,睡眠装置和钳位电路。 钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。
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公开(公告)号:US20060109028A1
公开(公告)日:2006-05-25
申请号:US11314236
申请日:2005-12-22
申请人: Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehia Ismail
发明人: Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehia Ismail
IPC分类号: H03K19/173
CPC分类号: G06F13/4072 , Y02D10/14 , Y02D10/151
摘要: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
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公开(公告)号:US20060061382A1
公开(公告)日:2006-03-23
申请号:US10947765
申请日:2004-09-23
申请人: Yibin Ye , James Tschanz , Muhammad Khellah , Vivek De
发明人: Yibin Ye , James Tschanz , Muhammad Khellah , Vivek De
IPC分类号: H03K19/003
CPC分类号: H03K19/23
摘要: Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.
摘要翻译: 装置和系统以及方法和物品可以使用耦合到第一多个位输入和第二多个位输入的读出放大器来提供多数选举指示。
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公开(公告)号:US20060001103A1
公开(公告)日:2006-01-05
申请号:US10880988
申请日:2004-06-30
申请人: Maged Ghoneima , Muhammad Khellah , James Tschanz , Yibin Ye , Vivek De
发明人: Maged Ghoneima , Muhammad Khellah , James Tschanz , Yibin Ye , Vivek De
IPC分类号: H01L29/76 , H01L21/8238
CPC分类号: G06F13/4217 , G11C7/1048 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.
摘要翻译: 一种器件包括具有多个用于传输信号的电路路径的互连结构。 电路路径以不同的速度传送信号,以减少相邻电路路径之间的耦合电容效应。
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公开(公告)号:US20060184595A1
公开(公告)日:2006-08-17
申请号:US11059174
申请日:2005-02-16
申请人: James Tschanz , Mircea Stan , Muhammad Khellah , Yibin Ye , Vivek De
发明人: James Tschanz , Mircea Stan , Muhammad Khellah , Yibin Ye , Vivek De
IPC分类号: G06F15/00
CPC分类号: G06F13/4213 , H03K19/23 , H03M5/145 , Y02D10/14 , Y02D10/151
摘要: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
摘要翻译: 一般来说,在一个方面,本公开描述了一种包括代表性的多数选民门来分析多个位的位转换的装置。 分组的分类分析。 代表大多数选民门根据分析产生反转信号。 该装置进一步包括条件反相器将反相信号应用于多个位。
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公开(公告)号:US20050225459A1
公开(公告)日:2005-10-13
申请号:US10813084
申请日:2004-03-31
申请人: Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehea Ismail
发明人: Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehea Ismail
CPC分类号: G06F13/4072 , Y02D10/14 , Y02D10/151
摘要: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
摘要翻译: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号,并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电,并且第二驱动器可以由不同于第一电压的第二电压供电。
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