公开(公告)号：US20150371694A1

公开(公告)日：2015-12-24

申请号：US14308262

申请日：2014-06-18

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： YAN SOLIHIN

IPC: G11C11/02 ,  G06F9/46 ,  G06F15/80 ,  G06F12/08 ,  G06F1/32

CPC classification number: G06F9/466 ,  G06F1/3275 ,  G06F12/0813 ,  G06F12/0842 ,  G06F15/80 ,  G06F2212/1016 ,  G06F2212/283 ,  G11C11/161 ,  Y02D10/13 ,  Y02D10/14

Abstract: Technologies are generally described for systems, devices and methods relating to multicore processors. The multicore processors may include first and second tiles with first and second caches, respectively. The first cache may include first magnetoresistive random access memory (MRAM) cells with first storage characteristics. The second cache may include second MRAM cells with second storage characteristics different from the first storage characteristics. In some examples, an interconnect structure may be coupled to the first and second tiles and may be configured to provide communication between the first tile and the second tile. Methods for handling migration between tiles and cores are also described.

Abstract translation: 技术通常被描述为与多核处理器有关的系统，设备和方法。 多核处理器可以分别包括具有第一和第二高速缓存的第一和第二瓦片。 第一高速缓存可以包括具有第一存储特性的第一磁阻随机存取存储器（MRAM）单元。 第二高速缓存可以包括具有与第一存储特性不同的第二存储特性的第二MRAM单元。 在一些示例中，互连结构可以耦合到第一和第二瓦片，并且可以被配置为提供第一瓦片和第二瓦片之间的通信。 还描述了处理瓦片和芯之间的迁移的方法。

公开(公告)号：US20160210229A1

公开(公告)日：2016-07-21

申请号：US15080605

申请日：2016-03-25

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： YAN SOLIHIN

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F9/461 ,  G06F9/4856 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/123 ,  G06F2212/62

Abstract: Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.

Abstract translation: 这里通常描述了用于加速多核处理器中的高速缓存状态传输的技术。 多核处理器可以包括第一，第二和第三瓦片。 多核处理器可以启动在第一块从第一块到第二块的在第一块上执行的线程的迁移。 多核处理器可以确定要从第一块处的第一高速缓存传输的块的块地址到第二块处的第二高速缓存，并且识别第三块中的目录对应于块地址。 多核处理器可以更新目录以反映第二高速缓存共享块。 多核处理器可以将块从第一块中的第一高速缓存传送到第二块中的第二高速缓存，以有效地完成从第一块到第二块的线程的迁移。

公开(公告)号：US20170228259A1

公开(公告)日：2017-08-10

申请号：US15495126

申请日：2017-04-24

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： YAN SOLIHIN

IPC: G06F9/50 ,  G06F12/0806 ,  G06F9/48 ,  G06F12/0875

CPC classification number: G06F9/5033 ,  G06F9/4881 ,  G06F9/5027 ,  G06F11/34 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2209/5018 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62

Abstract: Technologies are generally described for methods and systems to assign threads in a multi-core processor. In an example, a method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.

公开(公告)号：US20160253212A1

公开(公告)日：2016-09-01

申请号：US14758404

申请日：2014-02-27

Applicant: Empire Technology Development LLC

Inventor： YAN SOLIHIN

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F9/5033 ,  G06F9/4881 ,  G06F9/5027 ,  G06F11/34 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0875 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62

Abstract: Technologies are generally described for methods and systems to assign threads in a multi-core processor. In an example, a method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.

Abstract translation: 一般来说，为在多核处理器中分配线程的方法和系统描述技术。 在一个示例中，在多核处理器中分配线程的方法可以包括确定与存储器控制器相关的数据，以响应于由第一核心和第二核心经历的高速缓存未命中而获取数据。 可以根据各个存储器控制器处理的高速缓存未命中的数量将线程分配给内核。 方法还可以包括确定线程是等待时间限制的或带宽​​限制的。 可以基于线程的确定将线程分配给内核作为延迟限制或带宽限制。 响应于将线程分配给核心，线程的数据可以存储在分配的内核中。

公开(公告)号：US20170004079A1

公开(公告)日：2017-01-05

申请号：US15268226

申请日：2016-09-16

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： YAN SOLIHIN

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0292 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/0223 ,  G06F12/023

Abstract: Technologies are generally described for methods and systems effective to implement a memory allocation accelerator. A processor may generate a request for allocation of a requested chunk of memory. The request may be received by a memory allocation accelerator configured to be in communication with the processor. The memory allocation accelerator may process the request to identify an address for a particular chunk of memory corresponding to the request and may return the address to the processor.

Abstract translation: 通常描述有效实现内存分配加速器的方法和系统的技术。 处理器可以产生对所请求的存储器块的分配的请求。 该请求可以被配置为与处理器通信的存储器分配加速器来接收。 存储器分配加速器可以处理该请求以识别与该请求对应的特定存储块的地址，并且可以将该地址返回给处理器。

公开(公告)号：US20150186186A1

公开(公告)日：2015-07-02

申请号：US14657716

申请日：2015-03-13

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： YAN SOLIHIN

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/50 ,  G06F9/5005 ,  G06F2209/5018 ,  G06F2209/503

Abstract: Technologies are generally described for a method, device and architecture effective to allocate resources. In an example, the method may include associating first and second resources with first and second resource identifiers and mapping the first and resource identifiers to first and second sets of addresses in a memory, respectively. The method may include identifying that the first resource is at least partially unavailable. The method may include mapping the second resource identifier to at least one address of the first set of addresses in the memory when the first resource is identified as at least partially unavailable. The method may include receiving a request for the first resource, wherein the request identifies a particular address of the addresses in the first set of addresses. The method may include analyzing the particular address to identify a particular resource and allocating the request to the particular resource.

Abstract translation: 技术通常描述为有效分配资源的方法，设备和架构。 在一个示例中，该方法可以包括将第一和第二资源与第一和第二资源标识符相关联，并且将第一和第二资源标识符分别映射到存储器中的第一和第二组地址。 该方法可以包括识别第一资源至少部分不可用。 该方法可以包括当第一资源被识别为至少部分不可用时，将第二资源标识符映射到存储器中的第一组地址的至少一个地址。 该方法可以包括接收对第一资源的请求，其中该请求标识第一组地址中的地址的特定地址。 该方法可以包括分析特定地址以识别特定资源并将该请求分配给特定资源。

公开(公告)号：US20150242240A1

公开(公告)日：2015-08-27

申请号：US14710307

申请日：2015-05-12

Applicant: Empire Technology Development LLC

Inventor： YAN SOLIHIN

IPC: G06F9/48 ,  G06F9/50 ,  G06F12/08

CPC classification number: G06F9/4881 ,  G06F1/12 ,  G06F1/324 ,  G06F1/3287 ,  G06F9/5011 ,  G06F9/5088 ,  G06F12/0842 ,  G06F2212/6042 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/32

Abstract: Technologies are generally described for a multi-processor core and a method for transferring threads in a multi-processor core. In an example, a multi-core processor may include a first group including a first core and a second core. A first sum of the operating frequencies of the cores in the first group corresponds to a first total operating frequency. The multi-core processor may further include a second group including a third core. A second sum of the operating frequencies of the cores in the second group may correspond to a second total operating frequency that is substantially the same as the first total operating frequency. A hardware controller may be configured in communication with the first, second and third core. A memory may be configured in communication with the hardware controller and may include an indication of at least the first group and the second group.

Abstract translation: 技术通常被描述用于多处理器核心和用于在多处理器核心中传送线程的方法。 在一个示例中，多核处理器可以包括包括第一核和第二核的第一组。 第一组中的芯的工作频率的第一和对应于第一总操作频率。 多核处理器还可以包括包括第三核的第二组。 第二组中的芯的工作频率的第二和可以对应于与第一总操作频率基本相同的第二总工作频率。 硬件控制器可以被配置为与第一，第二和第三核心通信。 可以将存储器配置为与硬件控制器通信，并且可以包括至少第一组和第二组的指示。

公开(公告)号：US20150220437A1

公开(公告)日：2015-08-06

申请号：US14687452

申请日：2015-04-15

Applicant: Empire Technology Development LLC

Inventor： YAN SOLIHIN

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/082 ,  G06F12/122 ,  G06F12/123 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/621 ,  Y02D10/13

Abstract: Technologies are generally described for a cache coherence directory in multi-processor architectures. In an example, a directory in a die may receive a request for a particular block. The directory may determine a block aging threshold relating to a likelihood that data blocks, including the particular data block, are stored in one or more caches in the die. The directory may further analyze a memory to identify a particular cache indicated as storing the particular data block and identify a number of cache misses for the particular cache. The directory may identify a time when an event occurred for the particular data block and determine whether to send the request for the particular data block to the particular cache based on the aging threshold, the time of the event, and the number of cache misses.

Abstract translation: 通常在多处理器架构中针对高速缓存一致性目录描述技术。 在一个示例中，管芯中的目录可以接收对特定块的请求。 目录可以确定与包括特定数据块的数据块存储在管芯中的一个或多个高速缓存中的可能性相关的块老化阈值。 目录可以进一步分析存储器以识别指示为存储特定数据块的特定高速缓存并且识别特定高速缓存的多个高速缓存未命中。 目录可以识别特定数据块发生事件的时间，并且基于老化阈值，事件的时间和高速缓存未命中的数量来确定是否将特定数据块的请求发送到特定高速缓存。