公开(公告)号：US07091097B1

公开(公告)日：2006-08-15

申请号：US10933424

申请日：2004-09-03

Applicant: Eric N. Paton ,  Qi Xiang ,  Cyrus E. Tabery ,  Bin Yu ,  Robert B. Ogle

Inventor： Eric N. Paton ,  Qi Xiang ,  Cyrus E. Tabery ,  Bin Yu ,  Robert B. Ogle

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。 并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

公开(公告)号：US06743689B1

公开(公告)日：2004-06-01

申请号：US10341427

申请日：2003-01-14

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/458 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

Abstract: Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.

Abstract translation: 包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造 源/漏扩展的结晶和激活。 实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层 漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分 。

公开(公告)号：US06703277B1

公开(公告)日：2004-03-09

申请号：US10118437

申请日：2002-04-08

Applicant: Eric N. Paton ,  Bin Yu

Inventor： Eric N. Paton ,  Bin Yu

IPC: H01L218242

CPC classification number: H01L21/31691 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/3115 ,  H01L21/31155 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor device and a process for fabricating the device, the process including steps of depositing on the silicon substrate a layer comprising at least one high-K dielectric material, whereby a quantity of silicon dioxide is formed at an interface between the silicon substrate and the high-K dielectric material layer; depositing on the high-K dielectric material layer a layer of a metal; and diffusing the metal through the high-K dielectric material layer, whereby the metal reduces at least a portion of the silicon dioxide to silicon and the metal is oxidized to form a dielectric material having a K value greater than silicon dioxide. In another embodiment, the metal is implanted into the interfacial layer. A semiconductor device including such metal layer and implanted metal is also provided.

Abstract translation: 一种半导体器件和用于制造该器件的工艺，该工艺包括以下步骤：在硅衬底上沉积包含至少一种高K电介质材料的层，由此在硅衬底与硅衬底之间的界面处形成一定数量的二氧化硅 高K介电材料层; 在高K电介质材料层上沉积一层金属; 并且通过高K电介质材料层使金属扩散，由此金属将至少一部分二氧化硅还原为硅，并且金属被氧化以形成K值大于二氧化硅的电介质材料。 在另一个实施方案中，将金属注入界面层。 还提供了包括这种金属层和植入金属的半导体器件。

公开(公告)号：US06646307B1

公开(公告)日：2003-11-11

申请号：US10081362

申请日：2002-02-21

Applicant: Bin Yu ,  Eric N. Paton

Inventor： Bin Yu ,  Eric N. Paton

IPC: H01L2701

CPC classification number: H01L29/6675 ,  H01L29/78618 ,  H01L29/78648

Abstract: A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain. At least one of the bottom gate dielectric or the top gate dielectric is formed from a high-K material. A method of forming a double gate MOSFET is also disclosed where a semiconductor film used to form a body is recrystallized using a semiconductor substrate as a seed crystal.

Abstract translation: 双栅极MOSFET。 MOSFET包括设置在底栅电极上的底栅电极和底栅电介质。 半导体本体区域设置在底栅电介质和底栅电极之上，并且设置在源极和漏极之间。 顶栅电极设置在身体上。 顶栅电介质分离顶栅电极和主体，顶栅电极和底栅电极在主体内限定通道并置于源极和漏极之间。 底栅电介质或顶栅电介质中的至少一个由高K材料形成。 还公开了一种形成双栅极MOSFET的方法，其中用于形成本体的半导体膜使用半导体衬底作为晶种再结晶。

公开(公告)号：US07211489B1

公开(公告)日：2007-05-01

申请号：US10934378

申请日：2004-09-07

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

Abstract: The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel effects are prevented by the use of highly localized halo implant regions formed in the device channel. Highly localized halo implant regions are formed by a tilt pre-amorphization implant and a laser thermal anneal of the halo implant region.

Abstract translation: 本发明能够制造改进的高可靠性，高密度的半导体器件。 本发明通过减小诸如栅极沟道长度的半导体器件结构的尺寸来提供高密度半导体器件。 通过使用在器件通道中形成的高度局部化的注入区来防止短沟道效应。 通过倾斜预非晶化植入和晕圈植入区域的激光热退火形成高度局部化的注入区域。

公开(公告)号：US06812106B1

公开(公告)日：2004-11-02

申请号：US10341366

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

Abstract: Dopant deactivation of source/drain extensions during silicidation is reduced by forming deep source/drain regions using a disposable dummy gate as a mask, forming metal silicide layers on the deep source/drain regions, removing the dummy gate and then forming the source/drain extensions using laser thermal annealing. Embodiments include angular ion implantation, after removing the dummy gate, to form spaced apart pre-amorphized regions, ion implanting to form source/drain extension implants extending deeper into the substrate than the pre-amorphized regions, and then laser thermal annealing to activate the source/drain extensions having a higher impurity concentration at the main surface of the substrate than deeper into the substrate. Subsequent processing includes forming sidewall spacers, a gate dielectric layer and then the gate electrode.

Abstract translation: 通过使用一次性虚拟栅极作为掩模形成深源极/漏极区域，在深度源极/漏极区域形成金属硅化物层，去除虚拟栅极，然后形成源极/漏极 扩展使用激光热退火。 实施例包括角度离子注入，在去除虚拟栅极之后，形成间隔开的非晶化区域，离子注入以形成比预非晶化区域更深地延伸到衬底中的源极/漏极延伸植入物，然后激光热退火以激活 源/漏扩展在衬底的主表面具有较高的杂质浓度，而不是深入衬底。 随后的处理包括形成侧壁间隔物，栅介质层，然后形成栅电极。

公开(公告)号：US06680250B1

公开(公告)日：2004-01-20

申请号：US10145740

申请日：2002-05-16

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions. Because the recrystallization front velocity towards the substrate main surface is greater than the dopant atom velocity in the liquid substrate during laser thermal annealing, the junctions are not pushed down to the amorphous/crystalline silicon interface. Thus, end-of-range defects are located in a region below and spaced apart from the junctions, and the defects are not located in the activated source/drain regions. Junction leakage as a result of the end-of-range defects is thereby reduced.

Abstract translation: 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间在衬底上形成栅极电极和栅极氧化物。 然后将惰性掺杂剂注入衬底内以在衬底中形成非晶化的源极/漏极区域，延伸到明显大于预期结点深度的第一深度。 非晶化源极/漏极区域注入源极/漏极掺杂剂，使得掺杂剂延伸到衬底中的第二深度小于第一深度的第二深度，在第一深度之上，并且与在第一深度处产生的端部范围缺陷区域间隔开 非晶化过程。 激光热退火使非晶区再结晶，激活源极/漏极区并形成源极/漏极结。 因为朝向衬底主表面的再结晶前向速度大于激光热退火期间液体衬底中的掺杂剂原子速度，所以接合点不被推到非晶/硅晶界面。 因此，距离范围缺陷位于与接合点下方和间隔开的区域中，并且缺陷不位于活化的源极/漏极区域中。 因此，由于距离范围缺陷导致的结漏电减少。

公开(公告)号：US07351638B1

公开(公告)日：2008-04-01

申请号：US10021782

申请日：2001-12-18

Applicant: Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

Inventor： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂注入到衬底中并使用激光热退火激活掺杂剂。 在退火期间，激光器和衬底相对于彼此移动，并且激光器和衬底相对于彼此的运动在激活源极/漏极区域的一部分之间和在激活源极/漏极区域的另一部分之间不间断， 漏区。 来自激光器的每个脉冲可以分别照射源极/漏极区域的不同部分，并且激光器的斑点面积小于50毫米2。

公开(公告)号：US06780789B1

公开(公告)日：2004-08-24

申请号：US10230198

申请日：2002-08-29

Applicant: Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

Inventor： Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/268 ,  H01L21/31662 ,  H01L29/665 ,  H01L29/6659

Abstract: Ultra-thin gate oxides are formed by exposing the upper surface of a substrate to a pulsed laser light beam in an atmosphere containing oxygen. Embodiments include exposing a silicon substrate to a pulsed laser light beam at a radiant fluence of 0.1 to 0.8 joules/cm2 for 1 to 10 nanoseconds to form a gate oxide layer having a thickness of 3 Å to 8 Å, e.g., 3 Å to 5 Å.

Abstract translation: 通过在包含氧的气​​氛中将衬底的上表面暴露于脉冲激光束来形成超薄栅极氧化物。 实施例包括将硅衬底以0.1至0.8焦耳/平方厘米的辐射通量暴露于脉冲激光束1至10纳秒以形成厚度为3至8的栅极氧化物层，例如3 Å至5Å。

公开(公告)号：US06656749B1

公开(公告)日：2003-12-02

申请号：US10013354

申请日：2001-12-13

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Bin Yu ,  Cyrus E. Tabery ,  Qi Xiang

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Bin Yu ,  Cyrus E. Tabery ,  Qi Xiang

IPC: H01L2100

CPC classification number: H01L21/02675 ,  H01L21/2026 ,  H01L21/268 ,  H01L22/12 ,  H01L22/20 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes thermal annealing source/drain regions with a laser, measuring a depth of the source/drain regions, and adjusting a parameter of the laser used in the thermal annealing process. After the laser is adjusted, the source/drain regions are laser thermal annealed again until a desired depth of the source/drain regions is obtained. An apparatus for processing a semiconductor device includes a chamber, a laser, a measuring device, and a controller. The semiconductor device is positioned within the chamber for processing. The laser is used to laser thermal anneal the semiconductor device within the chamber. The measuring device measures a depth of source/drain regions in the semiconductor device when the semiconductor device is within the chamber, and the controller receives measurement information from the measuring device and adjusts parameters of the laser.

Abstract translation: 制造半导体器件的方法包括：用激光热退火源极/漏极区域，测量源极/漏极区域的深度，以及调整在热退火过程中使用的激光器的参数。 在调整激光器之后，源极/漏极区域被再次激光热退火，直到得到所需的源极/漏极区域的深度。 一种用于处理半导体器件的装置，包括腔室，激光器，测量装置和控制器。 半导体器件位于腔室内用于处理。 激光器用于对腔室内的半导体器件进行激光热退火。 当半导体器件在腔室内时，测量装置测量半导体器件中的源极/漏极区域的深度，并且控制器从测量装置接收测量信息并调整激光器的参数。