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    Strained silicon MOSFET having reduced leakage and method of its formation
    2.
    发明授权
    Strained silicon MOSFET having reduced leakage and method of its formation 有权
    应变硅MOSFET具有减少的泄漏和其形成方法

    公开(公告)号：US06924182B1

    公开(公告)日：2005-08-02

    申请号：US10642375

    申请日：2003-08-15

    申请人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    发明人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/76

    CPC分类号： H01L21/823878 ,  H01L21/76237 ,  H01L21/823807

    摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

    摘要翻译： 应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。 选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率 在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。 随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。 这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
    3.
    发明授权
    Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
    形成厚应变硅层的方法和掺入厚应变硅层的半导体结构

    公开(公告)号：US06730576B1

    公开(公告)日：2004-05-04

    申请号：US10335447

    申请日：2002-12-31

    申请人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    发明人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

    IPC分类号： H01L21762

    CPC分类号： H01L29/7833 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

    摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.

    摘要翻译： 应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。 在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。 两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。 因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。 在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

    Semiconductor with tensile strained substrate and method of making the same
    7.
    发明授权
    Semiconductor with tensile strained substrate and method of making the same 有权
    具有拉伸应变衬底的半导体及其制造方法

    公开(公告)号：US07001837B2

    公开(公告)日：2006-02-21

    申请号：US10346617

    申请日：2003-01-17

    申请人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    发明人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

    摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

    摘要翻译： 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

    Tensile strained substrate
    8.
    发明授权
    Tensile strained substrate 有权
    拉伸应变基材

    公开(公告)号：US07701019B2

    公开(公告)日：2010-04-20

    申请号：US11356606

    申请日：2006-02-17

    申请人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    发明人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

    摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

    摘要翻译： 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

    Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends
    9.
    发明授权
    Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends 有权
    形成栅极末端具有改善的阈值电压的应变硅MOSFET的方法

    公开(公告)号：US06893929B1

    公开(公告)日：2005-05-17

    申请号：US10641548

    申请日：2003-08-15

    申请人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Haihong Wang

    发明人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Haihong Wang

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10

    CPC分类号： H01L29/6659 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7842 ,  Y10S438/933

    摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.

    摘要翻译： 应变硅MOSFET中浅沟槽隔离的形成包括将掺杂剂注入到将要形成浅沟槽隔离的沟槽边缘处的应变硅层和硅锗层的伸出部分。 选择掺杂剂的导电类型与源极和漏极掺杂剂的导电类型相反。 注入的掺杂剂在应变硅层的突出部分中增加栅极端部之下的阈值电压Vt，使得其大致等于或大于MOSFET的其余部分的阈值电压。 所产生的应变硅MOSFET在栅极端部下方表现出减小的漏电流。