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    Data serializer
    1.
    发明授权
    Data serializer 有权

    公开(公告)号：US10129016B2

    公开(公告)日：2018-11-13

    申请号：US14542251

    申请日：2014-11-14

    Applicant: FINISAR CORPORATION

    Inventor： The'Linh Nguyen ,  Daniel K. Case

    IPC: H04L7/033 ,  H04J3/06 ,  H04L7/00 ,  H04L25/14 ,  H04J3/04 ,  H03L7/08 ,  H03M9/00

    Abstract: A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.

    DATA SERIALIZER
    3.
    发明申请
    DATA SERIALIZER 审中-公开
    数据串行

    公开(公告)号：US20150139252A1

    公开(公告)日：2015-05-21

    申请号：US14542251

    申请日：2014-11-14

    Applicant: FINISAR CORPORATION

    Inventor： The'Linh Nguyen ,  Daniel K. Case

    IPC: H04L7/033 ,  H04L7/00 ,  H04J3/06

    CPC classification number: H04L7/0331 ,  H03L7/0807 ,  H03M9/00 ,  H04J3/047 ,  H04J3/0635 ,  H04L7/0041 ,  H04L7/033 ,  H04L25/14

    Abstract: A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.

    Abstract translation: 串行器电路可以包括恢复电路，调整电路和多路复用器电路。 恢复电路可以被配置为以第一频率接收第一数据信号，以使用第一数据信号产生第一频率的第一时钟信号，并且基于第一时钟信号重新计算第一数据信号，以产生重定时 第一数据信号。 调整电路可以被配置为接收第二数据信号并基于第一时钟信号重新计时第二数据信号，以产生重新定时的第二数据信号。 复用器电路可以被配置为对重新定时的第一数据信号和重定时的第二数据信号进行复用。

    Low power and compact area digital integrator for a digital phase detector
    4.
    发明授权
    Low power and compact area digital integrator for a digital phase detector 有权
    低功耗和紧凑型数字积分器，用于数字相位检测器

    公开(公告)号：US09014322B2

    公开(公告)日：2015-04-21

    申请号：US13757665

    申请日：2013-02-01

    Applicant: Finisar Corporation

    Inventor： The'Linh Nguyen ,  Steven Gregory Troyer ,  Daniel K. Case

    IPC: H03D3/24 ,  H04L7/00 ,  H04L7/033 ,  H03L7/093

    CPC classification number: H03L7/091 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/093 ,  H04L7/0016 ,  H04L7/033

    Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

    Abstract translation: 在示例性实施例中，锁相环电路可以包括用于接收参考信号和源信号的第一电路。 第一电路可以产生用于示出参考信号和源信号之间的相位差的校正信号。 锁相环可以包括用于接收校正信号的第二电路。 第二电路可以产生用于演示校正信号的相位到数字转换的数字信号。 锁相环可以包括用于接收数字信号的第三电路。 第三电路可以产生用于演示数字信号的转换电压的控制信号。 锁相环可以包括用于接收控制信号的第四电路。 第四电路可以响应于控制信号产生源信号。

    LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR
    5.
    发明申请
    LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR 有权

    公开(公告)号：US20160013800A1

    公开(公告)日：2016-01-14

    申请号：US14691558

    申请日：2015-04-20

    Applicant: FINISAR CORPORATION

    Inventor： The'Linh Nguyen ,  Steven Gregory Troyer ,  Daniel K. Case

    IPC: H03L7/091 ,  H04L7/00

    CPC classification number: H03L7/091 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/093 ,  H04L7/0016 ,  H04L7/033

    Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

    LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR
    6.
    发明申请
    LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR 有权
    用于数字相位检测器的低功率和紧凑型数字集成器

    公开(公告)号：US20130315349A1

    公开(公告)日：2013-11-28

    申请号：US13757665

    申请日：2013-02-01

    Applicant: FINISAR CORPORATION

    Inventor： The'Linh Nguyen ,  Steven Gregory Troyer ,  Daniel K. Case

    IPC: H04L7/00

    CPC classification number: H03L7/091 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/093 ,  H04L7/0016 ,  H04L7/033

    Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

    Abstract translation: 在示例性实施例中，锁相环电路可以包括用于接收参考信号和源信号的第一电路。 第一电路可以产生用于示出参考信号和源信号之间的相位差的校正信号。 锁相环可以包括用于接收校正信号的第二电路。 第二电路可以产生用于演示校正信号的相位到数字转换的数字信号。 锁相环可以包括用于接收数字信号的第三电路。 第三电路可以产生用于演示数字信号的转换电压的控制信号。 锁相环可以包括用于接收控制信号的第四电路。 第四电路可以响应于控制信号产生源信号。

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