Electronic component overlapping dice of unsingulated semiconductor wafer
    1.
    发明申请
    Electronic component overlapping dice of unsingulated semiconductor wafer 失效
    电子元件重叠的半导体晶片的重叠芯片

    公开(公告)号:US20020074653A1

    公开(公告)日:2002-06-20

    申请号:US09971981

    申请日:2001-10-04

    Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiments a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry. One particularly preferred mode of connection is by incorporating resilient, free-standing contact structures on the same semiconductor device, with the structures standing farther away from the semiconductor and the capacitor. Other useful connectors include providing similar resilient, free-standing contact structures on the other device, then positioning the semiconductor over the resilient contacts and securing the two devices together. A socket with such resilient structures is particularly useful for this application. In an alternative preferred embodiment, the capacitor and resilient contacts all are incorporated in the second device, such as a socket. In one aspect of the invention, the ancillary electrical component may include a travel stop structure which defines a minimum separation between the semiconductor and a substrate such as a printed circuit board.

    Abstract translation: 本发明提供了非常接近半导体器件的辅助电气部件,优选地直接安装在半导体器件上。 在一个优选实施例中,辅助电气部件是电容器。 在优选实施例中,端子设置在半导体器件上,使得电容器可以通过焊接或与导电环氧树脂直接电连接到端子。 在电源回路端子之间连接电容器可提供卓越的噪声和瞬态抑制。 电容器和有源电路之间的非常短的路径提供极低的电感,允许使用相对较小的电容器。 然后,半导体器件连接到诸如PC板的电子设备,用于进一步连接到其它电路。 一个特别优选的连接方式是通过在相同的半导体器件上并入弹性,独立的接触结构,其结构远离半导体和电容器。 其他有用的连接器包括在另一装置上提供类似的弹性,独立的接触结构,然后将半导体定位在弹性触点上并将两个装置固定在一起。 具有这种弹性结构的插座对于该应用特别有用。 在替代的优选实施例中,电容器和弹性触点都被并入第二装置,例如插座。 在本发明的一个方面,辅助电气部件可以包括限定半导体和诸如印刷电路板的基板之间的最小间隔的行进止动结构。

    Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
    3.
    发明申请
    Efficient parallel testing of semiconductor devices using a known good device to generate expected responses 失效
    使用已知的良好器件对半导体器件进行有效的并行测试以产生预期响应

    公开(公告)号:US20020175697A1

    公开(公告)日:2002-11-28

    申请号:US10208173

    申请日:2002-07-29

    CPC classification number: G01R31/3193 G01R31/31905

    Abstract: A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

    Abstract translation: 公开了一种用于测试集成电路器件的系统,其中测试器通过通道与已知的良好器件进行通信。 测试仪 - DUT接口电路用于监视通道,同时测试人员将数据作为测试序列的一部分写入已知的良好设备中的位置。 作为响应,接口电路将数据写入被测设备(DUT)中的每一个中的相应位置。 当测试仪从已知的良好设备(KGD)中的位置读取时,接口电路监视通道,并且响应于从被测设备中的相应位置读取的DUT数据和从KGD获得的预期响应之间的比较。

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