公开(公告)号：US5809333A

公开(公告)日：1998-09-15

申请号：US627988

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F13/28

摘要： The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has four main elements: a Direct Memory Access (DMA) controller, a hardware state machine, a bus controller, and a device controller. The device controller may be an IDE hard disk controller which is able to generate long streams of data in an intermittent fashion wherein any single stream of data is targeted to a number of different host memory locations. The device controller may also be an ECP parallel port controller which interfaces with a number of different peripheral devices over a parallel bus wherein each peripheral device appears to the system as a separate and independent data path.

摘要翻译： 本发明是具有外围设备总线母盘的台式个人计算机（PC）系统。 该系统有四个主要元件：直接存储器访问（DMA）控制器，硬件状态机，总线控制器和设备控制器。 设备控制器可以是IDE硬盘控制器，其能够以间歇方式产生长数据流，其中任何单个数据流被定向到多个不同的主机存储器位置。 设备控制器还可以是ECP并行端口控制器，其通过并行总线与多个不同的外围设备进行接口，其中每个外围设备作为独立和独立的数据路径出现在系统中。

公开(公告)号：US5905912A

公开(公告)日：1999-05-18

申请号：US627989

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.

摘要翻译： 本发明涉及一种通过通用列表处理器实现外围设备总线主控的系统和方法。 该系统由四个主要元件组成：总线控制器，DMA控制器，列表处理器和设备控制器。 该系统在两种操作模式下运行。 这两种模式来自两个不同的模块：DMA控制器和列表处理器。 第一种操作模式是与分布式DMA模型直接兼容的单缓冲传输模式。 在此模式下，DMA控制器内的分布式DMA寄存器被编程为传送一个连续的数据缓冲区。 第二种操作模式是多缓冲传输模式，它使用缓冲传输描述符的链表来对DMA控制器内的分布式DMA寄存器进行编程，并独立于软件启动传输。

公开(公告)号：US5774743A

公开(公告)日：1998-06-30

申请号：US627987

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/12 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F13/124

摘要： The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.

摘要翻译： 本发明是一种用于在移动计算机系统中实现外围设备总线主控的系统和方法。 该系统使用移动计算机系统的微控制器对DMA控制器进行编程。 DMA控制器将数据传送到移动计算机系统的存储器和从存储器传送数据。 耦合到微控制器和DMA控制器的总线控制器实现来自DMA控制器和微控制器的存储器数据传送请求。 设备控制器（IDE硬盘控制器或ECP并行端口控制器）也耦合到DMA控制器和微控制器。 设备控制器通过向DMA控制器装置传送数据并从DMA控制器装置传送数据来接收并响应来自微控制器的命令信号，并在传送完成时产生完成信号。

公开(公告)号：US5845151A

公开(公告)日：1998-12-01

申请号：US627992

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has a Direct Memory Access (DMA) controller for transferring data to and from the memory of the desktop PC system. A hardware state machine is used for programming the DMA controller, generating and sending command signals, and receiving completion status after the transfer of data is complete. A bus controller is used for implementing a memory data transfer request from the DMA controller means and said hardware state machine means. A device controller, either a Universal Serial Bus (USB) controller or an Infrared Data Association (IrDA) controller, is used for receiving and responding to the command signals from the hardware state machine means, transferring data to and from the DMA controller means, and generating and returning a completion status to the hardware state machine means after the transfer of data is complete.

摘要翻译： 本发明是具有外围设备总线母盘的台式个人计算机（PC）系统。 该系统具有直接存储器访问（DMA）控制器，用于向台式PC系统的存储器传送数据。 硬件状态机用于对DMA控制器进行编程，生成和发送命令信号，并在数据传输完成后接收完成状态。 总线控制器用于实现来自DMA控制器装置和所述硬件状态机装置的存储器数据传送请求。 使用通用串行总线（USB）控制器或红外数据协会（IrDA）控制器的设备控制器来接收和响应来自硬件状态机装置的命令信号，向DMA控制器装置传送数据和从DMA控制器装置传送数据， 并且在数据传送完成之后产生并返回到硬件状态机装置的完成状态。

公开(公告)号：US5774744A

公开(公告)日：1998-06-30

申请号：US627986

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4291 ,  G06F13/28

摘要： The present invention relates to a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the mobile computer system's microcontroller for programming a DMA controller, generating and sending command signals, and receiving completion status after transfer of data is complete. The micro-controller accesses a data buffer descriptor list. The data buffer descriptor list describes each data transfer that the micro-controller initiates, controls, and completes. The Direct Memory Access controller which is programmed by the micro-controller transfers data to and from a memory section of the mobile computer system. A bus controller is used for implementing a memory data transfer request from the DMA controller means and the micro-controller means. A device controller such as a Universal Serial Bus (USB) controller or an Infrared Data Association (IrDA) controller is used for receiving and responding to command signals from the micro-controller, transferring data to and from the DMA controller, and generating and returning a completion status to the micro-controller after the transfer of data is complete.

摘要翻译： 本发明涉及一种用于在移动计算机系统中实现外围设备总线主控的系统和方法。 该系统使用移动计算机系统的微控制器对DMA控制器进行编程，生成和发送命令信号，并在数据传输完成后接收完成状态。 微控制器访问数据缓冲区描述符列表。 数据缓冲区描述符列表描述了微控制器启动，控制和完成的每个数据传输。 由微控制器编程的直接存储器访问控制器将数据传送到移动计算机系统的存储器部分和从存储器部分传送数据。 总线控制器用于实现来自DMA控制器装置和微控制器装置的存储器数据传送请求。 使用诸如通用串行总线（USB）控制器或红外数据协会（IrDA）控制器的设备控制器来接收和响应来自微控制器的命令信号，向DMA控制器传送数据和从DMA控制器传送数据，以及生成和返回 数据传输完成后微控制器的完成状态。

公开(公告)号：US6012115A

公开(公告)日：2000-01-04

申请号：US901465

申请日：1997-07-28

申请人： Peter Chambers ,  Lonnie Goff ,  David R. Evoy ,  Mark Eidson

发明人： Peter Chambers ,  Lonnie Goff ,  David R. Evoy ,  Mark Eidson

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/426

摘要： A method and system that enables real-time peripheral devices to be connected to a computer system utilizing Universal Serial Bus architecture. The present invention empowers the computer system to perform an accurate determination of the moment in time a predetermined event occurred within a real-time peripheral device by utilizing the start of frame pulse transmitted from a USB host controller to peripheral devices connected to it. When a predetermined event occurs within a peripheral device, a first timer within the peripheral device starts incrementing to determine the amount of time that elapses until the next start of frame occurs. Once the next start of frame occurs, the first timer stops incrementing and stores the time before start of frame value. Every start of frame pulse causes a second timer located within the USB host controller to start incrementing. The USB host controller interrogates the peripheral device which transfers data to the host controller indicating that (1) an event occurred and (2) the time before start of frame value of the first timer. The USB host controller interrupts the host processor and transfers it the data related to the peripheral device. The processor retrieves the time after start of frame value from the second timer and sums it with the time before start of frame value of the first timer resulting in the time after event value, which is the elapsed time since the predetermined event occurred and the processor read the second timer.

摘要翻译： 一种使实时外围设备能够使用通用串行总线架构连接到计算机系统的方法和系统。 本发明使计算机系统通过利用从USB主机控制器发送到与其连接的外围设备的帧脉冲的开始来准确地确定在实时外围设备中发生的预定事件的时刻。 当在外围设备中发生预定事件时，外围设备内的第一定时器开始递增以确定经过的时间量直到下一帧开始发生。 一旦帧的下一个开始，第一个定时器停止递增并存储帧值开始之前的时间。 每帧帧脉冲启动使位于USB主机控制器内的第二个定时器开始递增。 USB主机控制器询问向主机控制器传送数据的外围设备，指示（1）事件发生，（2）第一定时器的帧值开始之前的时间。 USB主机控制器中断主机处理器并传输与外围设备相关的数据。 处理器从第二定时器检索帧值开始之后的时间，并将其与第一定时器的帧值开始之前的时间相加，导致事件值之后的时间，这是从预定事件发生起经过的时间，处理器 读第二个定时器。

公开(公告)号：US06226701B1

公开(公告)日：2001-05-01

申请号：US09400738

申请日：1999-09-21

申请人： Peter Chambers ,  Lonnie Goff ,  David R. Evoy ,  Mark Hidson

发明人： Peter Chambers ,  Lonnie Goff ,  David R. Evoy ,  Mark Hidson

IPC分类号： G06F1300

CPC分类号： G06F13/426

摘要： A method and system that enables real-time peripheral devices to be connected to a computer system utilizing Universal Serial Bus architecture. The present invention empowers the computer system to perform an accurate determination of the moment in time a predetermined event occurred within a real-time peripheral device by utilizing the start of frame pulse transmitted from a USB host controller to peripheral devices connected to it. When a predetermined event occurs within a peripheral device, a first timer within the peripheral device starts incrementing to determine the amount of time that elapses until the next start of frame occurs. Once the next start of frame occurs, the first timer stops incrementing and stores the time before start of frame value. Every start of frame pulse causes a second timer located within the USB host controller to start incrementing. The USB host controller interrogates the peripheral device which transfers data to the host controller indicating that (1) an event occurred and (2) the time before start of frame value of the first timer. The USB host controller interrupts the host processor and transfers it the data related to the peripheral device. The processor retrieves the time after start of frame value from the second timer and sums it with the time before start of frame value of the first timer resulting in the time after event value, which is the elapsed time since the predetermined event occurred and the processor read the second timer.

摘要翻译： 一种使实时外围设备能够使用通用串行总线架构连接到计算机系统的方法和系统。 本发明使计算机系统通过利用从USB主机控制器发送到与其连接的外围设备的帧脉冲的开始来准确地确定在实时外围设备中发生的预定事件的时刻。 当在外围设备中发生预定事件时，外围设备内的第一定时器开始递增以确定经过的时间量直到下一帧开始发生。 一旦帧的下一个开始，第一个定时器停止递增并存储帧值开始之前的时间。 每帧帧脉冲启动使位于USB主机控制器内的第二个定时器开始递增。 USB主机控制器询问向主机控制器传送数据的外围设备，指示（1）事件发生，（2）第一定时器的帧值开始之前的时间。 USB主机控制器中断主机处理器并传输与外围设备相关的数据。 处理器从第二定时器检索帧值开始之后的时间，并将其与第一定时器的帧值开始之前的时间相加，导致事件值之后的时间，这是从预定事件发生起经过的时间，处理器 读第二个定时器。

公开(公告)号：US5958020A

公开(公告)日：1999-09-28

申请号：US960483

申请日：1997-10-29

申请人： David R. Evoy ,  Lonnie Goff ,  Peter Chambers ,  Mark Eidson

发明人： David R. Evoy ,  Lonnie Goff ,  Peter Chambers ,  Mark Eidson

IPC分类号： G06F13/42 ,  G06F13/14 ,  G06F13/20

CPC分类号： G06F13/4291

摘要： The system of the present invention comprises a system for implementing a real time capability in peripheral devices. The system of the present invention functions with a computer system including a processor, a memory, and a video controller, each coupled to a system bus. A USB (universal serial bus) controller is also coupled to the system bus for interfacing peripheral devices on a USB cable to the computer system. A first and second register are included in the USB controller for storing a controller frame number and a controller frame remaining, and a second and third register are included in the peripheral device for storing a device frame number and a device frame remaining. The peripheral device is coupled to the USB controller via a USB cable. A screen reference register is coupled to receive the controller frame number and the controller frame remaining from the USB controller and is coupled to receive a reference signal from a video controller. In response to receiving the reference signal, the screen reference register stores the controller frame number and the controller frame remaining. The peripheral device transmits the device frame number and the device frame remaining to the computer system in response to the occurrence of an event. The controller frame remaining and the controller frame number are subsequently compared with the device frame remaining and the device frame number to determine a computer system time (e.g., a real time) of the occurrence of the event.

摘要翻译： 本发明的系统包括用于在外围设备中实现实时能力的系统。 本发明的系统具有包括处理器，存储器和视频控制器的计算机系统，每个都耦合到系统总线。 USB（通用串行总线）控制器也耦合到系统总线，用于将USB电缆上的外围设备连接到计算机系统。 第一和第二寄存器被包括在USB控制器中，用于存储控制器帧号和控制器帧，并且第二和第三寄存器被包括在用于存储设备帧号和设备帧的外围设备中。 外围设备通过USB电缆连接到USB控制器。 耦合屏幕参考寄存器以接收来自USB控制器的控制器帧号和控制器帧，并且耦合以从视频控制器接收参考信号。 响应于接收到参考信号，屏幕参考寄存器存储控制器帧号并且剩余控制器帧。 外围设备响应于事件的发生将设备帧号和剩余的设备帧发送到计算机系统。 随后将剩余的控制器帧和控制器帧号与剩余的设备帧和设备帧号进行比较，以确定事件发生的计算机系统时间（例如，实时）。

公开(公告)号：US5475854A

公开(公告)日：1995-12-12

申请号：US187960

申请日：1994-01-28

申请人： Joseph A. Thomsen ,  Franklyn H. Story ,  David R. Evoy ,  W. Henry Potts ,  Brian N. Fall ,  Hrushikesh Nalubola

发明人： Joseph A. Thomsen ,  Franklyn H. Story ,  David R. Evoy ,  W. Henry Potts ,  Brian N. Fall ,  Hrushikesh Nalubola

IPC分类号： G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/14

CPC分类号： G06F13/385 ,  G06F13/32 ,  G06F13/423

摘要： A serial bus Input/Output (I/O) system has multiple I/O devices which are all connected in daisy-chain fashion on a serial bus. These I/O devices service peripherals that may generate different interrupt requests or DMA requests to the system controller. These requests are encoded, serialized and transmitted to the system controller on the serial bus, allowing the system controller to service a large number of interrupt requests and DMA requests via the serial bus with a very small number of external pins.

摘要翻译： 串行总线输入/输出（I / O）系统具有多个I / O设备，均以菊花链方式连接在串行总线上。 这些I / O设备服务可能会向系统控制器产生不同的中断请求或DMA请求的外围设备。 这些请求被编码，串行化并传输到串行总线上的系统控制器，允许系统控制器通过具有极少数量的外部引脚的串行总线来服务大量的中断请求和DMA请求。

公开(公告)号：US5740452A

公开(公告)日：1998-04-14

申请号：US624169

申请日：1996-03-29

申请人： Franklyn H. Story ,  David R. Evoy

发明人： Franklyn H. Story ,  David R. Evoy

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： The present invention relates to a system and method for passing Industry Standard Architecture (ISA) legacy interrupts across Peripheral Component Interconnect (PCI) connectors. The system interconnects a plurality of PCI devices coupled to a PCI bus such that a last interrupt pin of each of the plurality of PCI devices are coupled together in a directly bussed manner to provide a serial interrupt signal line. The remainder of the interrupt pins of each of the plurality of PCI devices are coupled together in a barber pole manner.

摘要翻译： 本发明涉及一种用于跨越跨周期组件互连（PCI）连接器传送工业标准架构（ISA）传统中断的系统和方法。 该系统将耦合到PCI总线的多个PCI设备互连，使得多个PCI设备中的每一个的最后一个中断引脚以直接总线方式耦合在一起以提供串行中断信号线。 多个PCI设备中的每一个的其余中断引脚以理智极点方式耦合在一起。