公开(公告)号：US09875956B1

公开(公告)日：2018-01-23

申请号：US15276182

申请日：2016-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Daniel P. Greenberg ,  Eric W. Tremble

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/04 ,  H01L24/14 ,  H01L25/0657 ,  H01L2223/6644 ,  H01L2223/6688 ,  H01L2224/0401 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/14177 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: The present disclosure relates to interface structures and, more particularly, to integrated interface structures with both parallel and serial interfaces and methods of manufacture. The integrated interface structure includes: a substrate; a plurality of serial interface connections integrated on the substrate; and a plurality of parallel interface connections on the integrated substrate and within spaces between sets of the plurality of serial interface connections.

公开(公告)号：US20190287879A1

公开(公告)日：2019-09-19

申请号：US15921852

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC: H01L23/488 ,  H01L25/065

Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

公开(公告)号：US10714411B2

公开(公告)日：2020-07-14

申请号：US15921852

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC: H01L23/48 ,  H01L23/488 ,  H01L25/065

Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.