公开(公告)号：US12033934B2

公开(公告)日：2024-07-09

申请号：US17710647

申请日：2022-03-31

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Yu-Ying Lee

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L25/16

CPC分类号： H01L23/49838 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/32 ,  H01L24/81 ,  H01L25/167 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/02379 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/014

摘要： A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.

公开(公告)号：US20240178174A1

公开(公告)日：2024-05-30

申请号：US18070109

申请日：2022-11-28

申请人： SONOVA AG

发明人： Anwar Hashmi

IPC分类号： H01L23/00 ,  H04R25/00

CPC分类号： H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H04R25/609 ,  H01L24/13 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14177 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/014

摘要： An exemplary hearing device includes a housing and a chip package disposed within the housing. The chip package may comprise a printed circuit board, an integrated circuit configured to perform an electronic function associated with the hearing device, and a plurality of solder bumps on a bottom surface of the integrated circuit. The plurality of solder bumps may provide conductive connectivity between the integrated circuit and the printed circuit board. The plurality of solder bumps may comprise a first group of solder bumps located within a center region of the bottom surface of the integrated circuit and a second group of solder bumps located within a peripheral region of the bottom surface, the peripheral region surrounding the center region. All signals required for the integrated circuit to perform the electronic function may be provided by way of the first group of solder bumps.

公开(公告)号：US20240096834A1

公开(公告)日：2024-03-21

申请号：US18126767

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih Hsuan HSU ,  Chan-Chung CHENG ,  Chun-Chen LIU ,  Cheng-Hung CHEN ,  Peng-Ren CHEN ,  Wen-Hao CHENG ,  Jong-l MOU

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/81

摘要： A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.

公开(公告)号：US20240071972A1

公开(公告)日：2024-02-29

申请号：US17823162

申请日：2022-08-30

申请人： Micron Technology, Inc.

发明人： Hidenori Yamaguchi ,  Keizo Kawakita ,  Bang-Ning Hsu

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/11464 ,  H01L2224/11912 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14134 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/1431 ,  H01L2924/1436

摘要： Apparatus and methods are disclosed, including stacked die devices and systems. Example stacked die devices and methods include an array of interconnect pillars that includes more than one pillar height. Example stacked die devices and methods include an array of interconnect pillars that includes a pillar height distribution mapped to a known warpage profile.

公开(公告)号：US11916033B2

公开(公告)日：2024-02-27

申请号：US17588525

申请日：2022-01-31

申请人： AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.

发明人： Glenn Rinne ,  Daniel Richter

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L23/49816 ,  H01L24/81 ,  H01L2224/06051 ,  H01L2224/06177 ,  H01L2224/119 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14141 ,  H01L2224/14151 ,  H01L2224/14153 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/81815 ,  H01L2924/10156 ,  H01L2924/15311 ,  H01L2224/119 ,  H01L21/78 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/13016 ,  H01L2924/00012 ,  H01L2224/14177 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/13014 ,  H01L2924/00012 ,  H01L2224/14154 ,  H01L2924/00012 ,  H01L2224/14177 ,  H01L2224/14154 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

摘要： Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

公开(公告)号：US20230337552A1

公开(公告)日：2023-10-19

申请号：US17722292

申请日：2022-04-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Corrado P. Mancini ,  David Lokken-Toyli

IPC分类号： H01L39/04 ,  H01L23/00 ,  H01L39/24 ,  H03F19/00 ,  H05K1/18

CPC分类号： H01L39/045 ,  H01L24/16 ,  H01L24/14 ,  H01L39/2493 ,  H03F19/00 ,  H05K1/181 ,  H01L2224/16225 ,  H01L2224/14177

摘要： A superconducting electrical device includes one or more traveling-wave parametric amplifiers (TWPAs) on a chip that is electrically connected to a wiring layer of a substrate. The electrical connection of the chip to the wiring layer of the substrate includes, for each of the one or more TWPAs, a signal bump-bond between the TWPA and the substrate. There is a peripheral ring of ground bumps around the signal bump between the TWPA and the substrate.

公开(公告)号：US20180047692A1

公开(公告)日：2018-02-15

申请号：US15233271

申请日：2016-08-10

申请人： Amkor Technology, Inc.

发明人： Glenn Rinne ,  Daniel Richter

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/06051 ,  H01L2224/06177 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14141 ,  H01L2224/14151 ,  H01L2224/14153 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/81815 ,  H01L2924/10156 ,  H01L2924/15311 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

公开(公告)号：US20180033757A1

公开(公告)日：2018-02-01

申请号：US15720127

申请日：2017-09-29

申请人： Renesas Electronics Corporation

发明人： Akira YAJIMA

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01022 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/01073 ,  H01L2924/0496 ,  H01L2924/01046 ,  H01L2924/01044 ,  H01L2924/01078 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00

摘要： In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved.

公开(公告)号：US20170133297A1

公开(公告)日：2017-05-11

申请号：US15414061

申请日：2017-01-24

申请人： STMicroelectronics (Crolles 2) SAS ,  SOCPRA Sciences et Génie S.E.C.

发明人： Louis-Michel Collin ,  Luc Guy Frechette ,  Sandrine Lhostis

IPC分类号： H01L23/42 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

CPC分类号： H01L23/42 ,  H01L21/31116 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/4875 ,  H01L21/4878 ,  H01L21/52 ,  H01L21/54 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/3157 ,  H01L23/3672 ,  H01L23/473 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49568 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14051 ,  H01L2224/14151 ,  H01L2224/14152 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/14517 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/27462 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29015 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/30151 ,  H01L2224/30152 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/37002 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/1415

摘要： An assembly includes an integrated circuit chip and a plate with at least one heat removal channel arranged between the chip and the plate. Metal sidewalls are formed to extend from one surface of the chip to an opposite surface of the plate. The assembly is encapsulated in a body that includes an opening extending to reach the channel. The plate may be one of an interposer, an integrated circuit chip, a support of surface-mount type, or a metal plate.

公开(公告)号：US09589921B2

公开(公告)日：2017-03-07

申请号：US14773817

申请日：2014-03-10

申请人： PS4 Luxco S.a.r.l. ,  Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

发明人： Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/12 ,  H01L21/56 ,  H01L21/66 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC分类号： H01L24/17 ,  H01L21/561 ,  H01L22/32 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/025 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/10734 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

摘要： In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.

摘要翻译： 在一个半导体器件中，半导体芯片具有设置在其主表面上的第一和第二焊盘电极，覆盖半导体芯片的主表面的绝缘膜，布置在绝缘膜之间的再布线层和多​​个外部端子 设置在绝缘膜的顶部。 第一焊盘电极和第二焊盘电极的平面尺寸彼此不同，并且第一焊盘电极和第二焊盘电极经由重新布线层连接到多个外部端子中的任何一个。