公开(公告)号：US20190287879A1

公开(公告)日：2019-09-19

申请号：US15921852

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC: H01L23/488 ,  H01L25/065

Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

公开(公告)号：US10714411B2

公开(公告)日：2020-07-14

申请号：US15921852

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC: H01L23/48 ,  H01L23/488 ,  H01L25/065

Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

公开(公告)号：US10475677B2

公开(公告)日：2019-11-12

申请号：US15682704

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tian Shen ,  Anil Kumar ,  Yuncheng Song ,  Kong Boon Yeap ,  Ronald G. Filippi, Jr. ,  Linjun Cao ,  Seungman Choi ,  Cathryn J. Christiansen ,  Patrick R. Justison

IPC: H01L21/67 ,  G01R3/00 ,  G01R31/12 ,  H01L21/66 ,  G01R31/28

Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

公开(公告)号：US20190066812A1

公开(公告)日：2019-02-28

申请号：US15685667

申请日：2017-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kong Boon Yeap ,  Tian Shen ,  Ronald Gene Filippi, JR. ,  Seungman Choi ,  Linjun Cao

IPC: G11C17/18 ,  G11C17/16

Abstract: An e-fuse structure including a circuit having an e-fuse operably coupling the circuit to a power source, and a redundant circuit for operably coupling the power source in response to opening of the e-fuse, wherein the e-fuse opens in response to a time-dependent dielectric breakdown (TDDB) percolation current in proximity to the circuit migrating through the e-fuse. A method of programming such an e-fuse structure is also disclosed.

公开(公告)号：US20190067056A1

公开(公告)日：2019-02-28

申请号：US15682704

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tian Shen ,  Anil Kumar ,  Yuncheng Song ,  Kong Boon Yeap ,  Ronald G. Filippi, JR. ,  Linjun Cao ,  Seungman Choi ,  Cathryn J. Christiansen ,  Patrick R. Justison

IPC: H01L21/67 ,  G01R3/00 ,  G01R31/12 ,  H01L21/66

Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.