公开(公告)号：US09575115B2

公开(公告)日：2017-02-21

申请号：US13649699

申请日：2012-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nathaniel R. Chadwick ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Kirk D. Peterson ,  Andrew A. Turner

IPC: G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2872 ,  G01R31/2831 ,  G01R31/2894 ,  H01L22/14 ,  H01L22/20

Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.

Abstract translation: 一种系统和方法对集成电路器件进行排序。 根据使用制造设备的集成电路设计，在晶片上制造集成电路器件。 该设计生产的集成电路器件根据制造工艺变化相同设计和执行不同。 集成电路设备在使用时可用于一系列环境条件。 在集成电路器件上进行测试。 每个设备单独预测环境最大值。 环境最大值包括每个设备在给定故障率以上执行时不得超过的环境条件。 基于为每个设备预测的环境最大值，为每个集成电路设备分配多个等级中的至少一个。 基于分配给每个设备的等级，将集成电路设备提供给具有不同环境条件的不同服务形式。

公开(公告)号：US09413169B2

公开(公告)日：2016-08-09

申请号：US14243295

申请日：2014-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H02H9/042

Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.

Abstract translation: 提供静电放电保护的电路和方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，被配置为选择性地将定时电路的节点与电源钳位装置连接的传输门，以及 控制电路与节点耦合。 控制电路被配置为基于电容器是否有缺陷来控制传输门。 如果定时电路中的电容器有故障并且相关的芯片被供电，则定时电路可以被去激活。 或者，如果定时电路中的电容器没有故障，则定时电路可以被激活。

公开(公告)号：US09536870B2

公开(公告)日：2017-01-03

申请号：US14977737

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/06 ,  G06F17/50 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L27/0262 ,  G06F17/5063 ,  G06F17/5072 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66121 ,  H01L29/66393 ,  H01L29/7408 ,  H01L29/7412 ,  H01L29/742 ,  H01L29/7436 ,  H01L29/861

Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

Abstract translation: 公开了一种静电放电保护电路。 一种制造半导体结构的方法包括在n阱中形成包括n阱体接触和阳极之间的第一多个指状物的半导体可控整流器，以及p阱体接触件和 阴极在p阱中。

公开(公告)号：US09263402B2

公开(公告)日：2016-02-16

申请号：US14554643

申请日：2014-11-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li

IPC: H01L21/00 ,  H01L23/60 ,  H01L27/02 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L23/60 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.