公开(公告)号：US20190088764A1

公开(公告)日：2019-03-21

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Steven BENTLEY ,  Puneet Harischandra SUVARNA ,  Chanro PARK ,  Min Gyu SUNG ,  Lars LIEBMANN ,  Su Chen FAN ,  Brent ANDERSON

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20180226505A1

公开(公告)日：2018-08-09

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok KIM ,  Hiroaki NIIMI ,  Hoon KIM ,  Puneet Harischandra SUVARNA ,  Steven BENTLEY ,  Jody A. FRONHEISER

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US20180108776A1

公开(公告)日：2018-04-19

申请号：US15295338

申请日：2016-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra SUVARNA

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: A vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or combination(s) thereof. The vertical transistors can be realized by providing a semiconductor substrate, forming stressed fin(s) of vertical transistor(s) acting as vertical transistor channels, the stressed fin(s) being lattice mismatched at one or more interfaces and being stressed from below, above, sidewalls or combination(s) thereof.