公开(公告)号：US20170047404A1

公开(公告)日：2017-02-16

申请号：US14825949

申请日：2015-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven BENTLEY ,  Rohit GALATAGE

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/205

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract translation: 完全III-V半导体或Si基晶体管的源极/漏极包括可以与沟道晶格匹配的底部阻挡层，宽带隙III-V材料的下层和较窄带隙的顶层 III-V材料，下层和顶层之间的组成渐变层从宽带隙材料逐渐过渡到窄带隙材料。

公开(公告)号：US20190115444A1

公开(公告)日：2019-04-18

申请号：US15783270

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven BENTLEY ,  Rohit GALATAGE ,  Puneet Harischandra Suvarna

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/516 ,  H01L21/28079 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/535 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.

公开(公告)号：US20170047425A1

公开(公告)日：2017-02-16

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven BENTLEY ,  Jody FRONHEISER ,  Xin MIAO ,  Joseph WASHINGTON ,  Pierre MORIN

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

Abstract translation: 提供了一种执行早期PTS植入和在体或鳍通道下形成缓冲层以控制沟道中的掺杂并且产生的体或鳍器件的方法。 实施例包括在基板中形成凹部; 在所述凹部的底表面下方形成PTS层; 在所述凹部的底表面和侧表面上形成缓冲层; 在缓冲层上和邻近缓冲层上形成沟道层; 并对通道，缓冲器和PTS层进行退火。

公开(公告)号：US20190088764A1

公开(公告)日：2019-03-21

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Steven BENTLEY ,  Puneet Harischandra SUVARNA ,  Chanro PARK ,  Min Gyu SUNG ,  Lars LIEBMANN ,  Su Chen FAN ,  Brent ANDERSON

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20180145073A1

公开(公告)日：2018-05-24

申请号：US15786164

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven BENTLEY ,  Bipul C. PAUL

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

公开(公告)号：US20160190289A1

公开(公告)日：2016-06-30

申请号：US14883045

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem AKARVARDAR ,  Steven BENTLEY

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/32134 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/785

Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.

Abstract translation: 提供了制造晶体管结构的方法，所述方法包括：形成具有上翅片部分和下翅片部分的翅片结构，所述上翅片部分包括牺牲材料; 在翅片上形成栅极结构; 选择性地去除所述上翅片部分以在所述门结构和所述下翅片部分之间形成隧道; 以及在隧道中提供通道材料以限定栅极结构的沟道区域。 牺牲材料可以是可以选择性地蚀刻而不蚀刻下部翅片部分的材料的材料。 可以进一步提供沟道材料以形成晶体管结构的源极和漏极区域，这可能导致无连接的FinFET结构。

公开(公告)号：US20180226505A1

公开(公告)日：2018-08-09

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok KIM ,  Hiroaki NIIMI ,  Hoon KIM ,  Puneet Harischandra SUVARNA ,  Steven BENTLEY ,  Jody A. FRONHEISER

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US20180138046A1

公开(公告)日：2018-05-17

申请号：US15351747

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven BENTLEY ,  Ruilong XIE

IPC: H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/265

CPC classification number: H01L21/28123 ,  H01L21/26513 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

公开(公告)号：US20150340289A1

公开(公告)日：2015-11-26

申请号：US14687300

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Steven BENTLEY

IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/161 ,  H01L21/02 ,  H01L29/165 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/161 ,  H01L29/165

Abstract: Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.

Abstract translation: 提供制造一个或多个半导体鳍片结构的方法，其包括：提供包括第一半导体材料的衬底结构; 在所述衬底结构上方提供散热片堆叠，所述散热片堆叠包括至少一个包括第二半导体材料的半导体层; 在所述散热片堆叠和所述基板结构上沉积保形膜; 以及使用至少部分地将所述散热片堆叠作为掩模来蚀刻所述衬底结构，以便于限定所述一个或多个半导体鳍片结构。 共形保护膜在蚀刻衬底结构期间保护散热片堆叠的至少一个半导体层的侧壁免受蚀刻。 作为一个示例，第一半导体材料可以是或包括硅，第二半导体材料可以是或包括硅锗，并且在一个示例中，保形膜可以是氮化硅。