公开(公告)号：US20170221764A1

公开(公告)日：2017-08-03

申请号：US15014150

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-gyu SUNG ,  Ruilong XIE ,  Chanro PARK

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US20160322260A1

公开(公告)日：2016-11-03

申请号：US14699122

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Sukwon HONG ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/823431 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481

Abstract: The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.

Abstract translation: 本申请涉及光学平坦化层蚀刻工艺。 实施例包括形成由电介质层分离的翅片; 在每个翅片的每一侧上的电介质层中形成凹槽，每个凹槽用于金属栅极; 在每个凹部的每一侧上形成侧壁间隔物; 在每个凹部和每个翅片的顶表面上沉积高k电介质衬垫; 在高k电介质层上沉积金属衬垫; 在所述电介质层的顶表面上沉积非共形有机层（NCOL）以夹紧每个凹部的顶部; 在NCOL上放置OPL和ARC; 在第一区域中的电介质层的一部分和凹部上蚀刻OPL，ARC和NCOL; 并且蚀刻所述凹部的所述部分以除去存在于所述凹部的所述部分的每个凹部的底部的残留NCOL。

公开(公告)号：US20160254158A1

公开(公告)日：2016-09-01

申请号：US14634483

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-Gyu SUNG ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517

Abstract: Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, at least two gate structures encompassing a portion of the raised structures, each gate structure including a gate opening lined with dielectric material and partially filled with work function material, a portion of the work function material being recessed. The co-fabrication further includes creating at least one conformal barrier layer in one or more and less than all of the gate openings, filling the gate openings with conductive material, and modifying the work function of at least one and less than all of the filled gate structures.

Abstract translation: 共同制造具有不同阈值电压的非平面（即，三维）半导体器件包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个凸起半导体结构，至少两个栅极结构， 每个栅极结构包括一个衬有介电材料并部分填充有功函材料的栅极开口，一部分功函材料被凹入。 共同制造还包括在一个或多个且少于所有的栅极开口中产生至少一个共形阻挡层，用导电材料填充栅极开口，以及修改至少一个且小于所有填充的栅极开口的功函数 门结构。

公开(公告)号：US20160126141A1

公开(公告)日：2016-05-05

申请号：US14531743

申请日：2014-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoon KIM ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Abstract translation: 用于形成具有用于减少穿通漏电的封盖层的FinFET的方法包括提供具有设置在半导体衬底上的半导体衬底和鳍的中间半导体结构。 覆盖层设置在翅片上方，并且隔离填充物设置在覆盖层上。 去除隔离填充物和覆盖层的一部分以露出翅片的上表面部分。 突出层和鳍的下部限定了界面偶极层势垒，所述覆盖层的一部分可操作以提供增加的负电荷或增加与所述鳍相邻的正电荷，以减少与不具有 盖层。

公开(公告)号：US20180138279A1

公开(公告)日：2018-05-17

申请号：US15351893

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Lars Wolfgang LIEBMANN ,  Hoon KIM

IPC: H01L29/417 ,  H01L29/772 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.

公开(公告)号：US20180130889A1

公开(公告)日：2018-05-10

申请号：US15345137

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/45 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/31051 ,  H01L21/32053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/45 ,  H01L29/665

Abstract: A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

公开(公告)号：US20170256455A1

公开(公告)日：2017-09-07

申请号：US15599026

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-gyu SUNG ,  Ruilong XIE ,  Chanro PARK

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US20180226505A1

公开(公告)日：2018-08-09

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok KIM ,  Hiroaki NIIMI ,  Hoon KIM ,  Puneet Harischandra SUVARNA ,  Steven BENTLEY ,  Jody A. FRONHEISER

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US20180096895A1

公开(公告)日：2018-04-05

申请号：US15284110

申请日：2016-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.

公开(公告)号：US20170053836A1

公开(公告)日：2017-02-23

申请号：US14830245

申请日：2015-08-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

Abstract translation: 一种方法包括提供具有第一和第二多个翅片的基底，其上设置有第一至少一个介电材料，去除第一介电材料的上部以暴露第一和第二多个翅片的上部，去除 第一介电材料从第二多个翅片的下部分暴露以暴露第二多个翅片的下部，在第二多个翅片的至少上部暴露部分和下部暴露部分上沉积第二至少一个电介质材料， 第一多个翅片的上暴露部分，去除第二介电材料以暴露第一和第二多个翅片的上部，并且其中第一介电材料不同于第二介电材料。 所得到的结构可以用作nFET和pFET。