公开(公告)号：US20160126141A1

公开(公告)日：2016-05-05

申请号：US14531743

申请日：2014-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoon KIM ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Abstract translation: 用于形成具有用于减少穿通漏电的封盖层的FinFET的方法包括提供具有设置在半导体衬底上的半导体衬底和鳍的中间半导体结构。 覆盖层设置在翅片上方，并且隔离填充物设置在覆盖层上。 去除隔离填充物和覆盖层的一部分以露出翅片的上表面部分。 突出层和鳍的下部限定了界面偶极层势垒，所述覆盖层的一部分可操作以提供增加的负电荷或增加与所述鳍相邻的正电荷，以减少与不具有 盖层。

公开(公告)号：US20190088764A1

公开(公告)日：2019-03-21

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Steven BENTLEY ,  Puneet Harischandra SUVARNA ,  Chanro PARK ,  Min Gyu SUNG ,  Lars LIEBMANN ,  Su Chen FAN ,  Brent ANDERSON

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20180138279A1

公开(公告)日：2018-05-17

申请号：US15351893

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Lars Wolfgang LIEBMANN ,  Hoon KIM

IPC: H01L29/417 ,  H01L29/772 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.

公开(公告)号：US20180130889A1

公开(公告)日：2018-05-10

申请号：US15345137

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/45 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/31051 ,  H01L21/32053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/45 ,  H01L29/665

Abstract: A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

公开(公告)号：US20190067115A1

公开(公告)日：2019-02-28

申请号：US15683968

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Laertis ECONOMIKOS ,  Ruilong XIE ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L29/66

Abstract: A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with an etch selective dielectric later. Lateral etching of the dielectric layer after removing remaining portions of the sacrificial gate can be used to increase the distance between the gate cut (isolation) structure and an adjacent fin relative to methods that do not perform a step of trimming the dielectric layer.

公开(公告)号：US20160322260A1

公开(公告)日：2016-11-03

申请号：US14699122

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Sukwon HONG ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/823431 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481

Abstract: The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.

Abstract translation: 本申请涉及光学平坦化层蚀刻工艺。 实施例包括形成由电介质层分离的翅片; 在每个翅片的每一侧上的电介质层中形成凹槽，每个凹槽用于金属栅极; 在每个凹部的每一侧上形成侧壁间隔物; 在每个凹部和每个翅片的顶表面上沉积高k电介质衬垫; 在高k电介质层上沉积金属衬垫; 在所述电介质层的顶表面上沉积非共形有机层（NCOL）以夹紧每个凹部的顶部; 在NCOL上放置OPL和ARC; 在第一区域中的电介质层的一部分和凹部上蚀刻OPL，ARC和NCOL; 并且蚀刻所述凹部的所述部分以除去存在于所述凹部的所述部分的每个凹部的底部的残留NCOL。

公开(公告)号：US20160204265A1

公开(公告)日：2016-07-14

申请号：US15077153

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Kwan-Yong LIM ,  Sukwon HONG

IPC: H01L29/78 ,  H01L21/225 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract translation: 提供了制造包括FinFET结构的电路结构的方法，包括：提供衬底和在衬底上方具有第一阈值电压的第一材料以及具有低于第一材料之上的第一阈值电压的第二阈值电压的第二材料; 形成具有由所述第一材料形成的基部翅片部分和由所述第二材料形成的上部翅片部分的翅片; 在所述翅片上提供栅极结构以形成一个或多个FinFET结构，其中所述栅极结构至少缠绕在所述上鳍部分上并具有低于所述第一阈值电压并高于所述第二阈值电压的工作电压，使得所述上翅片 部分限定一个或多个FinFET结构的通道尺寸。 还提供了包括FinFET结构的电路结构，其中FinFET结构具有仅由其上翅部分限定的均匀通道尺寸。

公开(公告)号：US20180096895A1

公开(公告)日：2018-04-05

申请号：US15284110

申请日：2016-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.

公开(公告)号：US20170062429A1

公开(公告)日：2017-03-02

申请号：US15172201

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Neeraj TRIPATHI

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/66818

Abstract: A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

Abstract translation: 提供了形成翅片衬垫的方法和所得到的装置。 实施例包括在衬底的负沟道场效应晶体管（nFET）和正沟道场效应晶体管（pFET）区域上形成硅（Si）鳍，每个Si散热片具有氮化硅（SiN）帽; 在Si翅片和SiN帽上形成SiN衬垫; 在所述pFET区域上形成块掩模; 去除nFET区域中的SiN衬垫; 去除pFET区域中的块掩模; 在Si散热片上形成扩散阻挡衬垫; 在Si散热片之上和之间形成介电层; 将电介质层平坦化到nFET区域中的SiN帽; 并使介电层凹陷以暴露Si散热片的上部。

公开(公告)号：US20170053836A1

公开(公告)日：2017-02-23

申请号：US14830245

申请日：2015-08-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

Abstract translation: 一种方法包括提供具有第一和第二多个翅片的基底，其上设置有第一至少一个介电材料，去除第一介电材料的上部以暴露第一和第二多个翅片的上部，去除 第一介电材料从第二多个翅片的下部分暴露以暴露第二多个翅片的下部，在第二多个翅片的至少上部暴露部分和下部暴露部分上沉积第二至少一个电介质材料， 第一多个翅片的上暴露部分，去除第二介电材料以暴露第一和第二多个翅片的上部，并且其中第一介电材料不同于第二介电材料。 所得到的结构可以用作nFET和pFET。