公开(公告)号：US09123568B2

公开(公告)日：2015-09-01

申请号：US14086563

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Richard Carter ,  Andy Wei

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/485 ,  H01L23/28

CPC classification number: H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.

Abstract translation: 半导体器件包括多个NMOS晶体管元件，每个NMOS晶体管元件均包括在第一有源区上方的第一栅极电极结构，多个第一栅电极结构中的至少两个包括第一封装堆叠，第一封装堆叠具有第一电介质盖层和第一侧壁 间隔堆叠 半导体器件还包括多个PMOS晶体管元件，每个PMOS晶体管元件包括在第二有源区上方的第二栅极电极结构，其中多个第二栅电极结构中的至少两个包括具有第二电介质盖层和 第二侧壁间隔堆叠。 另外，第一和第二侧壁间隔堆叠每个包括至少三个介电材料层，其中第一和第二侧壁间隔物叠层的三个介电材料层中的每一个包括相同的电介质材料。

公开(公告)号：US20140246735A1

公开(公告)日：2014-09-04

申请号：US13781907

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thilo Scheiper ,  Carsten Grass ,  Richard Carter ,  Martin Trentzsch

IPC: H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract translation: 这里公开了用于诸如晶体管的半导体器件的改进的金属栅极结构的各种实施例。 在本文公开的一个示例中，晶体管具有由位于半导体衬底上的栅极绝缘层，位于栅极绝缘层上的高k绝缘层，位于高k绝缘层上的氮化钛层组成的栅极结构 ，位于氮化钛层上的铝层和位于铝层上的多晶硅层。

公开(公告)号：US20130126980A1

公开(公告)日：2013-05-23

申请号：US13718158

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures.

Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和导电触点的各种方法以及包括该栅极结构和导电触点的装置。 一个示例性器件包括位于半导体衬底上方的多个栅极结构，位于栅极结构的相应侧壁附近的至少一个侧壁隔离物，以及在半导体衬底的源极/漏极区域中的金属硅化物区域，金属硅化物区域延伸 横向地接触定位在每个栅极结构附近的侧壁间隔件。 此外，该装置还包括位于多个栅极结构之间的导电触点，导电触点具有导电接触金属硅化物区域的下部分和位于下部部分上方的上部，其中下部分 横向宽于上部并且横向延伸，以便接近靠近每个门结构的侧壁间隔件。

公开(公告)号：US08872285B2

公开(公告)日：2014-10-28

申请号：US13781907

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Carsten Grass ,  Richard Carter ,  Martin Trentzsch

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract translation: 这里公开了用于诸如晶体管的半导体器件的改进的金属栅极结构的各种实施例。 在本文公开的一个示例中，晶体管具有由位于半导体衬底上的栅极绝缘层，位于栅极绝缘层上的高k绝缘层，位于高k绝缘层上的氮化钛层组成的栅极结构 ，位于氮化钛层上的铝层和位于铝层上的多晶硅层。

公开(公告)号：US08742510B2

公开(公告)日：2014-06-03

申请号：US13718158

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

IPC: H01L21/70 ,  H01L21/02 ,  H01L23/48 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures.

Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和导电触点的各种方法以及包括该栅极结构和导电触点的装置。 一个示例性器件包括位于半导体衬底上方的多个栅极结构，位于栅极结构的相应侧壁附近的至少一个侧壁隔离物，以及在半导体衬底的源极/漏极区域中的金属硅化物区域，金属硅化物区域延伸 横向地接触定位在每个栅极结构附近的侧壁间隔件。 此外，该装置还包括位于多个栅极结构之间的导电触点，导电触点具有导电接触金属硅化物区域的下部分和位于下部部分上方的上部，其中下部分 横向宽于上部并且横向延伸，以便接近靠近每个门结构的侧壁间隔件。

公开(公告)号：US20130280873A1

公开(公告)日：2013-10-24

申请号：US13793401

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Elke Erben ,  Martin Trentzsch ,  Richard Carter ,  Carsten Grass

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02181 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/28079 ,  H01L21/28194 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477

Abstract: When forming sophisticated circuit elements, such as transistors, capacitors and the like, using a combination of a conventional dielectric material and a high-k dielectric material, superior performance and reliability may be achieved by forming a hafnium oxide-based high-k dielectric material on a conventional dielectric layer with a preceding surface treatment, for instance using APM at room temperature. In this manner, sophisticated transistors of superior performance and with improved uniformity of threshold voltage characteristics may be obtained, while also premature failure due to dielectric breakdown, hot carrier injection and the like may be reduced.

Abstract translation: 当形成诸如晶体管，电容器等的复杂电路元件时，通过使用常规电介质材料和高k电介质材料的组合，可以通过形成基于氧化铪的高k电介质材料来实现优异的性能和可靠性 在具有前面表面处理的常规电介质层上，例如在室温下使用APM。 以这种方式，可以获得具有优异性能并具有改善的阈值电压特性均匀性的复杂晶体管，同时由于介电击穿，热载流子注入等而导致的过早故障也可能被降低。