公开(公告)号：US10079300B2

公开(公告)日：2018-09-18

申请号：US15426728

申请日：2017-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/1159 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/40111 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor circuit element includes a first semiconductor device positioned in and above a first active region of a semiconductor substrate and a second semiconductor device positioned in and above a second active region of the semiconductor substrate. The first semiconductor device includes a first gate structure having a first gate dielectric layer that includes a first high-k material, and the second semiconductor device includes a second gate structure having a second gate dielectric layer that includes a ferroelectric material that is different from the first high-k material.

公开(公告)号：US09508588B2

公开(公告)日：2016-11-29

申请号：US14527424

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Carsten Grass ,  Martin Trentzsch ,  Sören Jansen

IPC: H01L21/762 ,  H01L21/266 ,  H01L21/311

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括在第一器件区域和第二器件区域之间的隔离区域的半导体衬底。 隔离区域包括与第一器件区域相邻的第一部分和与第二器件区域相邻的第二部分。 该方法包括将隔离区域的第二部分选择性蚀刻到第二高度。 该方法在第一器件区域和第二器件区域上形成绝缘层。 所述方法还包括在所述隔离区域的所述第一器件区域和所述第一部分上选择性蚀刻所述绝缘层。 隔离区域的第一部分被蚀刻到基本上等于第二高度的第一高度。

公开(公告)号：US20170148919A1

公开(公告)日：2017-05-25

申请号：US15426728

申请日：2017-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor circuit element includes a first semiconductor device positioned in and above a first active region of a semiconductor substrate and a second semiconductor device positioned in and above a second active region of the semiconductor substrate. The first semiconductor device includes a first gate structure having a first gate dielectric layer that includes a first high-k material, and the second semiconductor device includes a second gate structure having a second gate dielectric layer that includes a ferroelectric material that is different from the first high-k material.

公开(公告)号：US20160126132A1

公开(公告)日：2016-05-05

申请号：US14527424

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Carsten Grass ,  Martin Trentzsch ,  Sören Jansen

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括在第一器件区域和第二器件区域之间的隔离区域的半导体衬底。 隔离区域包括与第一器件区域相邻的第一部分和与第二器件区域相邻的第二部分。 该方法包括将隔离区域的第二部分选择性蚀刻到第二高度。 该方法在第一器件区域和第二器件区域上形成绝缘层。 所述方法还包括在所述隔离区域的所述第一器件区域和所述第一部分上选择性蚀刻所述绝缘层。 隔离区域的第一部分被蚀刻到基本上等于第二高度的第一高度。

公开(公告)号：US08951877B2

公开(公告)日：2015-02-10

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US20140246735A1

公开(公告)日：2014-09-04

申请号：US13781907

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thilo Scheiper ,  Carsten Grass ,  Richard Carter ,  Martin Trentzsch

IPC: H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract translation: 这里公开了用于诸如晶体管的半导体器件的改进的金属栅极结构的各种实施例。 在本文公开的一个示例中，晶体管具有由位于半导体衬底上的栅极绝缘层，位于栅极绝缘层上的高k绝缘层，位于高k绝缘层上的氮化钛层组成的栅极结构 ，位于氮化钛层上的铝层和位于铝层上的多晶硅层。

公开(公告)号：US09337045B2

公开(公告)日：2016-05-10

申请号：US14458718

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Grass ,  Peter Baars

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28194 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element is formed on the basis of a replacement gate process replacing a dummy gate structure of a semiconductor device of the semiconductor circuit element by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a high-k material that is in the ferroelectric phase. In some illustrative embodiments herein, a semiconductor device is provided, the semiconductor device having a gate structure disposed over an active region of a semiconductor substrate. Herein, the gate structure comprises a spacer structure and a dummy gate structure which is replaced by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a ferroelectric high-k material.

Abstract translation: 本公开提供了一种形成半导体电路元件和半导体电路元件的方法，其中，基于替换栅极工艺形成半导体电路元件，替代栅极工艺通过栅极替代半导体电路元件的半导体器件的伪栅极结构 氧化物结构和栅电极材料，其中栅极氧化物结构包括处于铁电相中的高k材料。 在本文的一些说明性实施例中，提供半导体器件，该半导体器件具有设置在半导体衬底的有源区上方的栅极结构。 这里，栅极结构包括由栅极氧化物结构和栅电极材料代替的间隔结构和虚拟栅极结构，其中栅极氧化物结构包括铁电高k材料。

公开(公告)号：US09123827B2

公开(公告)日：2015-09-01

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324 ,  H01L21/283 ,  H01L21/02

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US20150200142A1

公开(公告)日：2015-07-16

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US20140264347A1

公开(公告)日：2014-09-18

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。