公开(公告)号：US09425052B2

公开(公告)日：2016-08-23

申请号：US14698103

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Jan Hoentschel ,  Steven Langdon

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/28 ,  H01L29/10 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/51

CPC classification number: H01L21/26506 ,  H01L21/266 ,  H01L21/2822 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517

Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.

Abstract translation: 复杂晶体管的性能和/或均匀性可以通过在形成复杂的高k金属栅电极结构之前在晶体管的有源区中引入碳物种来增强。 例如，在选择性地形成用于P沟道晶体管的阈值调节半导体材料之后，可以通过离子注入将碳物质并入P沟道晶体管和N沟道晶体管的有源区，而N的有源区 通道晶体管仍然被掩蔽。

公开(公告)号：US20140246735A1

公开(公告)日：2014-09-04

申请号：US13781907

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thilo Scheiper ,  Carsten Grass ,  Richard Carter ,  Martin Trentzsch

IPC: H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract translation: 这里公开了用于诸如晶体管的半导体器件的改进的金属栅极结构的各种实施例。 在本文公开的一个示例中，晶体管具有由位于半导体衬底上的栅极绝缘层，位于栅极绝缘层上的高k绝缘层，位于高k绝缘层上的氮化钛层组成的栅极结构 ，位于氮化钛层上的铝层和位于铝层上的多晶硅层。

公开(公告)号：US20140220759A1

公开(公告)日：2014-08-07

申请号：US14244611

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Abstract translation: 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括形成虚拟栅极结构，其包括具有侧壁并覆盖半导体衬底的伪栅极电极以及虚设栅电极的侧壁上的第一和第二侧壁间隔物。 该方法包括去除伪栅电极以形成由第一和第二侧壁间隔物限定的沟槽。 该方法移除第一侧壁间隔物的上部，并将一层金属沉积在沟槽中并在第一侧壁间隔物的剩余部分上方形成栅电极和互连。

公开(公告)号：US20140113419A1

公开(公告)日：2014-04-24

申请号：US13654849

申请日：2012-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski ,  Rolf Stephan

IPC: H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  Y02P80/30

Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.

Abstract translation: 在一个示例中，该方法包括在半导体衬底中形成多个隔离结构，其限定第一和第二有源区，其中将分别形成第一和第二晶体管器件，在衬底的表面上形成硬掩模层， 第一和第二有源区，其中所述硬掩模层包括碳，氟，氙或锗离子中的至少一种，执行第一蚀刻工艺以去除所述硬掩模层的一部分并暴露所述第一和第二有源区中的一个的表面 活性区域，在进行第一蚀刻工艺之后，在通过第一蚀刻工艺曝光的有源区的表面上形成沟道半导体材料，并且在形成沟道半导体材料之后，执行第二蚀刻工艺以除去 硬掩模层，其在第一蚀刻工艺期间未被除去。

公开(公告)号：US20130307112A1

公开(公告)日：2013-11-21

申请号：US13947793

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Thilo Scheiper

IPC: H01L29/861

CPC classification number: H01L29/8611 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/822 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L27/127 ,  H01L29/66136

Abstract: A substrate diode device having an anode and a cathode includes a doped well positioned in a bulk layer of an SOI substrate. A first doped region is positioned in the doped well, the first doped region being for one of the anode or the cathode, the first doped region having a first long axis and a second doped region positioned in the doped well. The second doped region is separate from the first doped region, the second doped region being for the other of the anode or the cathode, the second doped region having a second long axis that is oriented at an orientation angle with respect to the first long axis.

Abstract translation: 具有阳极和阴极的衬底二极管器件包括位于SOI衬底的体层中的掺杂阱。 第一掺杂区域位于掺杂阱中，第一掺杂区域用于阳极或阴极中的一个，第一掺杂区域具有位于掺杂阱中的第一长轴和第二掺杂区。 第二掺杂区域与第一掺杂区域分开，第二掺杂区域用于阳极或阴极中的另一个，第二掺杂区域具有第二长轴，其以相对于第一长轴线的取向角定向 。

公开(公告)号：US09490361B2

公开(公告)日：2016-11-08

申请号：US14192158

申请日：2014-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Thilo Scheiper

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7848

Abstract: Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.

Abstract translation: 通过在延伸到半导体衬底的腔中形成非平面MOSFET，可以避免MOSFETS中栅极和感应沟道长度的光刻限制。 栅极绝缘体和沟道区域靠近具有相对于半导体表面的角度α优选地约≥90度的空腔侧壁。 通道长度取决于空腔的底部深度以及与空腔相邻的源极或漏极区域的表面的深度。 相应的漏极或源极位于腔底。 空腔侧壁在其间延伸。 两个深度都不是光刻依赖的。 可以一贯形成非常短的通道，从而提高性能和制造成品率。 源极，漏极和栅极连接被带到相同的表面，使得可以容易地构造复杂的电路。 源区和漏区优选地外延形成，并且应变诱导材料可用于其中以改善沟道载流子迁移率。

公开(公告)号：US09490189B2

公开(公告)日：2016-11-08

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38 ,  H01L35/32 ,  G06F1/20 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US09082662B2

公开(公告)日：2015-07-14

申请号：US13968545

申请日：2013-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Stefan Flachowsky

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/1207

Abstract: When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

Abstract translation: 当形成复杂的SOI器件时，通过使用一个相同的注入掩模来形成衬底二极管和膜二极管，以确定相应阱区中的阱掺杂剂浓度。 因此，在进一步处理期间，可以独立于半导体层中的二极管的阱区实现任何晶体管元件的阱掺杂剂浓度。

公开(公告)号：US20140238045A1

公开(公告)日：2014-08-28

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US08759922B2

公开(公告)日：2014-06-24

申请号：US13959237

申请日：2013-08-05

Applicant: GlobalFoundries Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Thilo Scheiper

IPC: H01L29/78 ,  H01L27/01 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66507 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7845

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract translation: 半导体器件形成为没有栅极的完全硅化，并且独立调节栅极和源极/漏极区域中的硅化物。 实施例包括在基板上形成栅极，在栅极上形成氮化物盖，在栅极的每一侧形成源/漏区，在每个源/漏区中形成第一硅化物，在形成 第一硅化物，并且在去除氮化物盖之后，在源极/漏极区域和栅极中形成第二硅化物。 实施例包括通过在源极/漏极区上形成第一金属层并执行第一RTA来形成第一硅化物，以及通过在源极/漏极区域和栅极上形成第二金属层并执行第二RTA形成第二硅化物 。