公开(公告)号：US09064900B2

公开(公告)日：2015-06-23

申请号：US13936824

申请日：2013-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Matthias Goldbach ,  Martin Trentzsch

IPC: H01L29/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/7851 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0607 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract translation: 本公开提供了用于形成半导体器件结构的半导体器件结构和方法，其中场感应结构被设置为比翅片的高度尺寸低于翅片的有源部分，高度尺寸平行于法线方向延伸 形成有翅片的半导体衬底表面。 因此，励磁结构在有源部分下方实现永久场效应。 翅片的活动部分应理解为由栅极电介质覆盖的翅片的一部分。

公开(公告)号：US09508588B2

公开(公告)日：2016-11-29

申请号：US14527424

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Carsten Grass ,  Martin Trentzsch ,  Sören Jansen

IPC: H01L21/762 ,  H01L21/266 ,  H01L21/311

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括在第一器件区域和第二器件区域之间的隔离区域的半导体衬底。 隔离区域包括与第一器件区域相邻的第一部分和与第二器件区域相邻的第二部分。 该方法包括将隔离区域的第二部分选择性蚀刻到第二高度。 该方法在第一器件区域和第二器件区域上形成绝缘层。 所述方法还包括在所述隔离区域的所述第一器件区域和所述第一部分上选择性蚀刻所述绝缘层。 隔离区域的第一部分被蚀刻到基本上等于第二高度的第一高度。

公开(公告)号：US20150243789A1

公开(公告)日：2015-08-27

申请号：US14711029

申请日：2015-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Matthias Goldbach ,  Martin Trentzsch

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0607 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract translation: 本公开提供了用于形成半导体器件结构的半导体器件结构和方法，其中场感应结构被设置为比翅片的高度尺寸低于翅片的有源部分，高度尺寸平行于法线方向延伸 形成有翅片的半导体衬底表面。 因此，励磁结构在有源部分下方实现永久场效应。 翅片的活动部分应理解为由栅极电介质覆盖的翅片的一部分。

公开(公告)号：US08823138B1

公开(公告)日：2014-09-02

申请号：US13937332

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Matthias Goldbach ,  Martin Trentzsch

IPC: H01L29/00 ,  H01L49/02

CPC classification number: H01L28/20

Abstract: A semiconductor structure includes a resistor. The resistor includes a semiconductor region, a dielectric layer, a first electrical connection and a second electrical connection. The dielectric layer is provided on the semiconductor region and includes a high-k material having a greater dielectric constant than silicon dioxide. The dielectric layer includes a species creating fixed charges. A first electrical connection is provided at a first end of the semiconductor region and a second electrical connection is provided at a second end of the semiconductor region.

Abstract translation: 半导体结构包括电阻器。 电阻器包括半导体区域，电介质层，第一电连接和第二电连接。 电介质层设置在半导体区域上，并且包括具有比二氧化硅更大的介电常数的高k材料。 电介质层包括产生固定电荷的物质。 在半导体区域的第一端处提供第一电连接，并且在半导体区域的第二端设置第二电连接。

公开(公告)号：US20140264626A1

公开(公告)日：2014-09-18

申请号：US14174474

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Nicolas Sassiat ,  Jan Hoentschel ,  Martin Trentzsch ,  Carsten Grass

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7833

Abstract: The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer.

Abstract translation: 在一些方面，本公开提供了一种用于半导体器件的栅电极结构。 在本文的一些说明性实施例中，栅电极结构包括在半导体衬底的第一有源区上的第一高k电介质层和第一高k电介质层上的第二高k电介质层。 第一高k电介质层具有并入其中的金属物质，用于调节第一高k电介质层的功函数。

公开(公告)号：US20130280873A1

公开(公告)日：2013-10-24

申请号：US13793401

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Elke Erben ,  Martin Trentzsch ,  Richard Carter ,  Carsten Grass

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02181 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/28079 ,  H01L21/28194 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477

Abstract: When forming sophisticated circuit elements, such as transistors, capacitors and the like, using a combination of a conventional dielectric material and a high-k dielectric material, superior performance and reliability may be achieved by forming a hafnium oxide-based high-k dielectric material on a conventional dielectric layer with a preceding surface treatment, for instance using APM at room temperature. In this manner, sophisticated transistors of superior performance and with improved uniformity of threshold voltage characteristics may be obtained, while also premature failure due to dielectric breakdown, hot carrier injection and the like may be reduced.

Abstract translation: 当形成诸如晶体管，电容器等的复杂电路元件时，通过使用常规电介质材料和高k电介质材料的组合，可以通过形成基于氧化铪的高k电介质材料来实现优异的性能和可靠性 在具有前面表面处理的常规电介质层上，例如在室温下使用APM。 以这种方式，可以获得具有优异性能并具有改善的阈值电压特性均匀性的复杂晶体管，同时由于介电击穿，热载流子注入等而导致的过早故障也可能被降低。

公开(公告)号：US20160126132A1

公开(公告)日：2016-05-05

申请号：US14527424

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Carsten Grass ,  Martin Trentzsch ,  Sören Jansen

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括在第一器件区域和第二器件区域之间的隔离区域的半导体衬底。 隔离区域包括与第一器件区域相邻的第一部分和与第二器件区域相邻的第二部分。 该方法包括将隔离区域的第二部分选择性蚀刻到第二高度。 该方法在第一器件区域和第二器件区域上形成绝缘层。 所述方法还包括在所述隔离区域的所述第一器件区域和所述第一部分上选择性蚀刻所述绝缘层。 隔离区域的第一部分被蚀刻到基本上等于第二高度的第一高度。

公开(公告)号：US20140246735A1

公开(公告)日：2014-09-04

申请号：US13781907

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thilo Scheiper ,  Carsten Grass ,  Richard Carter ,  Martin Trentzsch

IPC: H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract translation: 这里公开了用于诸如晶体管的半导体器件的改进的金属栅极结构的各种实施例。 在本文公开的一个示例中，晶体管具有由位于半导体衬底上的栅极绝缘层，位于栅极绝缘层上的高k绝缘层，位于高k绝缘层上的氮化钛层组成的栅极结构 ，位于氮化钛层上的铝层和位于铝层上的多晶硅层。

公开(公告)号：US10163933B1

公开(公告)日：2018-12-25

申请号：US15676529

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Dünkel ,  Martin Trentzsch ,  Sven Beyer

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L29/51

Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

公开(公告)号：US10084057B2

公开(公告)日：2018-09-25

申请号：US15237794

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Martin Trentzsch ,  Stefan Flachowsky ,  Axel Henke

IPC: H03K3/01 ,  H01L29/51 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/516 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1159 ,  H01L27/1203 ,  H01L29/0642 ,  H01L29/40111 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/78391 ,  H01L29/78654

Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.