公开(公告)号：US20170229358A1

公开(公告)日：2017-08-10

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/544

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US10056306B2

公开(公告)日：2018-08-21

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  H01L23/544 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US09577023B2

公开(公告)日：2017-02-21

申请号：US13909464

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Dinh Dang ,  David A. DeMuynck ,  Sarah A. McTaggart ,  Gary L. Milo ,  Melissa J. Roma ,  Jeffrey L. Thompson ,  Thomas W. Weeks

IPC: H01F5/00 ,  H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract translation: 一种包括在第一电介质层中形成第一金属线的方法，所述第一金属线包括与第二垂直侧相对的第一垂直侧; 以及在所述第一电介质层上方的第二电介质层中形成第二金属线，所述第二金属线包括与第四垂直侧相反的第三垂直侧，其中所述第一垂直侧从所述第三垂直侧横向偏移第一预定 距离，第二垂直侧从第四垂直侧横向偏移第二预定距离，其中第一金属线和第二金属线彼此直接接触。