公开(公告)号：US09368420B2

公开(公告)日：2016-06-14

申请号：US14732689

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Wilfried E. Haensch ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/01 ,  H01L23/14 ,  H01L27/12 ,  H01L27/092 ,  H01L23/538 ,  H01L21/762

CPC classification number: H01L23/14 ,  H01L21/4846 ,  H01L21/7624 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/5387 ,  H01L27/092 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

公开(公告)号：US09577065B2

公开(公告)日：2017-02-21

申请号：US14707923

申请日：2015-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wilfried E. Haensch ,  Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L29/417 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66477 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78621

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract translation: 用于制造晶体管器件的线路器件的后端和方法包括其上形成有绝缘层的衬底和形成在绝缘层上的沟道层。 栅极结构形成在沟道层上。 在栅极结构的相对侧将掺杂剂注入沟道层的上部，以使用低温注入工艺形成浅的源极和漏极区。 在浅源极和漏极区上选择性地生长外延层，以使用低温等离子体增强化学气相沉积工艺在通道层上方和栅极结构上形成凸起区域，其中低温小于约400摄氏度。

公开(公告)号：US20160379986A1

公开(公告)日：2016-12-29

申请号：US15160482

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Wilfried E. Haensch

IPC: H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10867 ,  H01L21/845 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1207 ,  H01L29/0673 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/785

Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

公开(公告)号：US09484430B2

公开(公告)日：2016-11-01

申请号：US14720328

申请日：2015-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wilfried E. Haensch ,  Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L29/40 ,  H01L29/417 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66477 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78621

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.